# What happens when the chip enable active time limit is exceeded?

The datasheet of a FRAM chip (FM1608-120-P) says that "the device has a maximum /CE low time specification that must be satisfied". The datasheet does not state what the consequences are when this limit is exceeded. Chip enable must be pulled low in order for the address to be latched in.

The maximum active time for the chip enable pin as stated in the datasheet is 10,000ns.

What happens when this limit is exceeded? Does it damage the chip? Or does it simply mean that the output will become invalid?

• I finally looked at the right datasheet, I think. That's not the B part, but an obsolete part. Shouldn't you be using the B? There, /CE looks as though it can be grounded and just left there. – jonk May 29 '17 at 22:12
• @jonk the tCE time states the maximum time needed for the output data to be valid. I'm talking about tCA (Chip Enable Active Time), which has a minimum of 120ns (needed for output to be valid) and a maximum rating of 10,000ns, reason unknown. – uzumaki May 29 '17 at 22:14
• Yeah. I finally found the right datasheet, though it shows 2,000 and not 10,000 as the limit for $t_{CA}$. The B part doesn't have this limitation, it appears. I'm just guessing but perhaps the earlier part had a design limitation using a pre-charged but leaky capacitive section and they've changed it with the newer part so that issue has gone away. The newer part does exhibit a slightly higher standby dissipation that may be due to this change. I doubt any permanent harm in the older part, though. – jonk May 29 '17 at 22:18