I am using STM32VL discovery board(STM32f100rb6).. Using this code for USART setup (including baud-rate):

#include "main.h"
#include "LCD-HD44780.h"
void UART1_init(void)
    /* Enable GPIOA's Clock from APB2, Bit2->1  */
    RCC->APB2ENR |= BIT2;
    //Enable USART1 Clock
    RCC->APB2ENR |= BIT14;

    /* UART1 : UART1_RX: PA10 -> input Floating: (GPIOA_CRH -> reset state so leave it)*/

    /* UART1 : UART1_TX: PA9  -> alternate function push pull */
    GPIOA->CRH |= BIT4 | BIT5; //Output mode 50Mhz
    GPIOA->CRH |= BIT7; // Alternate function output Push-pull

    //Enable UART
    USART1->CR1 |= BIT13;
    //USART1->CR1 |= BIT15;
    //Word Lenght 8 bit reset mode
    //SET 1 STOP Bit reset mode
    // BaudRate config (baudrate=1200)-fclk=24MHz
    USART1->BRR = (uint32_t)(1250 << 4);
    //Enable Transmit,Send IDLE Frame as first data
    USART1->CR1 |= BIT3;
    while (!(USART1->SR && BIT7));//Wait until TXE is 1;
    while (!(USART1->SR && BIT6));//Wait until TC is 1;
    USART1->DR = 1;
    while (!(USART1->SR && BIT7));//Wait until TXE is 1;
    while (!(USART1->SR && BIT6));//Wait until TC is 1;

and this code for clocks setup:

#include "stm32f10x.h"
#include "custom.h"

void SystemInit(void)

    /* Enable HSI-RC Bit0->1 */
    RCC->CR |= BIT0;

    /* Set PLL Source As HSI/2 Bit 16->0 */
    RCC->CFGR &= ~BIT16;

    // Set PLLMUL to 6-> Bit 20 ->1 */
    RCC->CFGR |= BIT20;

    //Set SYSCLK Source As PLL bit 1 ->1
    RCC->CFGR |= BIT1;

    // Set AHB Prescalar to 8 bit[7:4]: 1010
    //RCC->CFGR |= (BIT5 | BIT7);

    /* Select HSI as System Clock */
    //RCC->CFGR &= ~BIT0 & ~BIT1; // OR Nothing (Reset State)

    /* Set AHPR prescalar as Bit7 ->0 */
    //RCC->CFGR &= ~BIT7; //Or reset state

    /* Set APB2 prescalar to 1 BIT13->0 */
    //RCC->CFGR &= ~BIT13;


need this:

#include <stdint.h>
#ifndef CUSTOM_H
#define CUSTOM_H
#define BIT0  (uint32_t)0x1
#define BIT1  (uint32_t)0x2
#define BIT2  (uint32_t)0x4
#define BIT3  (uint32_t)0x8
#define BIT4  (uint32_t)0x10
#define BIT5  (uint32_t)0x20
#define BIT6  (uint32_t)0x40
#define BIT7  (uint32_t)0x80
#define BIT8  (uint32_t)0x100
#define BIT9  (uint32_t)0x200
#define BIT10 (uint32_t)0x400
#define BIT11 (uint32_t)0x800
#define BIT12 (uint32_t)0x1000
#define BIT13 (uint32_t)0x2000
#define BIT14 (uint32_t)0x4000
#define BIT15 (uint32_t)0x8000
#define BIT16 (uint32_t)0x10000
#define BIT17 (uint32_t)0x20000
#define BIT18 (uint32_t)0x40000
#define BIT19 (uint32_t)0x80000
#define BIT20 (uint32_t)0x100000
#define BIT21 (uint32_t)0x200000
#define BIT22 (uint32_t)0x400000
#define BIT23 (uint32_t)0x800000
#define BIT24 (uint32_t)0x1000000
#define BIT25 (uint32_t)0x2000000
#define BIT26 (uint32_t)0x4000000
#define BIT27 (uint32_t)0x8000000
#define BIT28 (uint32_t)0x10000000
#define BIT29 (uint32_t)0x20000000
#define BIT30 (uint32_t)0x40000000
#define BIT31 (uint32_t)0x80000000

char* cprintf(int integer);
int strlenght(char str[20]);
char int2char(int i);
char* revstr(char* str);

I am arranged to have 24Mhz as USART1-fclk and baud-rate-1200, but when I analyze output by seleae logic-analyzer,found out actual baud-rate is 400 not 1200.(images are appended). baud-rate=1200 enter image description here same one by baud-rate=400: enter image description here where is the mistake??

  • 2
    \$\begingroup\$ How sure are you of the system clock? Something like direct use of an 8 MHz crystal without the PLL enabled would explain your factor-of-three error. \$\endgroup\$ May 30, 2017 at 23:46
  • \$\begingroup\$ according to SystemInit(),I configured PCLK2=24MHz using of Internal RC 8MHz oscillator clock source..It seems true ,where is the mistake? \$\endgroup\$ May 31, 2017 at 5:34
  • \$\begingroup\$ For Baudrate calculation I used RM0008 document (Page 803/1137 -chapter 27.3.4) and according that USARTDIV=Fclk/(16*Baudrate),so USARTDIV=1250 \$\endgroup\$ May 31, 2017 at 5:39
  • \$\begingroup\$ You need to find a way to verify that the clock is actually 24 MHz. \$\endgroup\$ May 31, 2017 at 5:50
  • \$\begingroup\$ I think find out mistake.. I commented all configuration on SystemInit(), so result is the same! @ Chris Stratton: You are right.. Fclk is wrong.. I try more and inform.. \$\endgroup\$ May 31, 2017 at 6:51

1 Answer 1


Finally solved. Must enable PLLON bit on RCC-CR. but after all configuration. If you set PLLON bit, no configuration will set. actually we just using 8MHz clock.


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