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what is the difference between a master slave flipflop and edge triggered flip flop in terms of circuitry and performance?like the aim they serve i.e. one transition per clockpulse of the final output, is same then how are they different?

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There is a lot of confusion regarding the differences here. A master-slave flip flop is edge triggered. Please don't confuse latches with flip flops -- it will make everything seem very arbitrary. A FF is just two back to back latches with opposite phase clocks -- the first is the master and the second is the slave. The transparency windows are near-mutually exclusive so a lock and dam type flow is created.

See my previous answers for more in depth information. Also please know that both answers here already are wrong and will simply lead to confusion.

what is ff

difference bw latches and ff

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  • \$\begingroup\$ A flip-flop is defined by its CIRCUIT STRUCTURE, NOT by its inputs. A master-slave flip-flop is NOT, 100% of the time, edge-triggered. A flip-flop by definition is "A two-stage latch in a master-slave configuration." Period. You can have async/sync flip-flops just as you can have async/sync latches. Both are forms of asynchronous sequential circuits (aka state-machines). How many times are you going to post incorrect information to people? Go read "The Electronics Handbook" by Jerry Whitaker. He provides crystal clear definitions and descriptions. \$\endgroup\$ – mrbean Jan 3 at 1:00
  • \$\begingroup\$ @mrbean: i think you are confusing monolithic devices like 74xx series with the actual circuit implementation. As I said in my answer, a FF is two back to back latches with opposite phases. It is always more accurate to analyze a FF as two latches. If the clocks are well controlled, it is completely reasonable to treat it as "edge triggered". If there is some overlap b/w master being open and slave being open, it is more like a FF with some input-output transparency. All the nonsense about sync/async latches is just the controlling circuitry between the clock and the latch. \$\endgroup\$ – jbord39 Apr 12 at 14:56
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Some of the master-slave flipflops are "ones catching" types. If the input level for changing state is present at any time (before the setup time), for any length of time (greater than the minimum specified PW) before the clock edge, the flipflop will toggle. Edge triggered flipflops ignore any state that was present before the setup time. I think most master-slaves are (were?) negative pulse triggered too. I haven't used a non-positive edge triggered flipflop, counter, register, etc. in more than 50 years. It's no exaggeration to say the 7474 and its followers changed everything.

The data sheet from TI for the SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J-K FLIP-FLOPS WITH CLEAR available at http://www.ti.com/lit/ds/symlink/sn74ls107a.pdf shows usage of the terms. description from data sheet

The pertinent part of it is the description section, above. The '107 is called a positive pulse triggered flip-flop, and the last sentence in the first paragraph explains why. "Inputs must be stable," means it's a ones-catching flip-flop. (More properly it would be called opposite-state-catching.) Of course the outputs change on an edge of the clock, but the data inputs can't change from the time the clock is high until that edge. "Pulse triggered" sounds better than "ones catching" so that's what is used in data sheets. "Edge triggered" means not "ones catching." The only thing that matters is the data state before the edge. The 'LS107A (edge triggered) is an improved version of the '107. In most applications it's a direct replacement. There might be places where you might want the '107 instead, I suppose. None come to mind.

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  • \$\begingroup\$ Anyone that gave downvotes please give your flawed reason along with your apology. \$\endgroup\$ – toiler Jun 21 '17 at 1:40
  • \$\begingroup\$ I'll give you an upvote +1! \$\endgroup\$ – mrbean Jan 3 at 22:29
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Not going to answer the question, but push you in the right direction.

A master-slave flip-flop can be made from TWO edge triggered D flip-flops.

schematic

simulate this circuit – Schematic created using CircuitLab

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