Is there a standard model for estimating the additional clocking latency which needs to be applied based on product interconnects?
For example: Lets say a DDR memory has a switching time of 1 ns.
However, if I want to put that product on a board, the signal path goes from a microcontroller pin through to a PCB board, across a trace, through some connector, through another trace, to a package pin, and along a wire bond before it hits the actual die of the memory.
Each of those parts in the signal path have propagation delays, parasitic capacitances, and inductances that might form which degrades the signal and lengthens the time before a signal can reach its max, so I would need to add more clock time the longer that path is.
Is there a standard for how such setups are evaluated, to estimate what those capacitances/impedances are? I'm aware that traces on PCB have their propagation time determined by the length of the trace and the permittivity of the substrate, but I'm not sure how other considerations factor in.