the use of 220microFarad capacitor which is connected with the centre tap of the transformer
This reduces ripples in the power supply. Current is drawn from the 12 V supply in pulses. C2 reduces the impedance of the supply at the switching frequency, thereby reducing the voltage excursions caused by the current pulses.
How is feedback circuit working, Is it a window comparator circuit?
No, it's a plain old comparator circuit, just that there are two of them. Note that each of the comparators U3C and U2B have the same inputs. They will therefore produce the same outputs. The positive input comes from a reference voltage produced by the pot labeled "50%", then filtered by R10 and C7. This is meant to be a fixed DC level, adjusted so that ultimately the desired DC level is achieved after rectifying the transformer output.
I haven't looked it up, but from the circuit it seems clear that the comparators have open collector outputs. Multiple comparators with outputs wired together therefore perform a AND function. The comparators U4D and U1A produce pulses of opposite polarity to ultimately drive the push-pull switching elements. The outputs of U3C and U2B simply ground these signals, thereby keeping the switches off, when the feedback signal is above the threshold.
Use of transistor, I mean the Square wave which we are getting can be directly fed to the Mosfet but why have we used transistors?
This question makes no sense since MOSFETs are transistors.
The circuitry between a comparator output and its FET gate is a crude FET driver. It takes the open collector output of the comparator and drives the FET gate with it actively in both direction.
When the U4D output goes off, it goes up due to R1. That is at the high impedance of 10 kΩ, which would switch the FET slowly. Q3 is used in emitter follower configuration, and acts as a impedance buffer. It reduces the 10 kΩ drive by its gain. If the gain of Q3 is 100, for example, then the FET gate is being driven high by about 100 Ω instead of the original 10 kΩ.
That works for the rising edge, but does nothing for the falling edge, which would only drive the FET gate low due to R2. D1 fixes this by allowing a direct discharge path for the FET gate charge when the comparator output is actively driven low.