verilog - altera fpga "error pin x has multiple drivers due to the non-tri-state driver"

Question

I have a 32 bit parellel IO interface (PIO) defined in a NIOS II soft processor. It is for a 32 pin connector on a board.

I instantiate the NIOS in a top level verilog module called test below.

On the connector pins 0:4 are JTAG pins and 5:31 are bi-directional pins that I want to be able to set direction and state.

The FT_ADB0-4 pins go to a FDTI chip for the jtag.

My question is how can I correctly write verilog for this.

I want all 32 bins on CON_0 to be available to the 32 bit PIO in the NIOS. So that when I set for example bit 10 in the PIO I am indeed controlling pin 10 on the connector.

In the code below I get the error

Error (13076): The pin "CON_0[0]" has multiple drivers due to the non-tri-state driver "FT_ADB1"

module test2 (  CLOCK_50B, CON_0, FT_ADB0, FT_ADB1, FT_ADB2, FT_ADB3, FT_ADB4);

// Basic clocks
input  CLOCK_50B;

// CON_0 parallel ports
inout  [31:0]  CON_0;

// FT2332.. used for JTAG !
input  FT_ADB0; //TCK
input  FT_ADB1; //TDI
output FT_ADB2; //TDO
input  FT_ADB3; //TMS
input  FT_ADB4; //NRESET 

assign CON_0[2] = (1) ? FT_ADB0 : 'bz; //TCK
assign CON_0[0] = (1) ? FT_ADB1 : 'bz; //TDI
assign FT_ADB2 = CON_0[1]; //TDO output from DUT drives FTDI
assign CON_0[3] = (1) ? FT_ADB3 : 'bz; //TMS

assign CON_0[4] = 'bz;


// Instantiate the Nios II system module generated by the Qsys tool:

    nios2 u0 (
        .clk_clk       (CLOCK_50B),       //  clk.clk
        .CON_0_export   (CON_0)            //  CON_0.in_port

    );

endmodule

Answer 1

Create an internal signal CON_0_nios which maps to the NIOS port and is driven by CON_0 whereas it only drives CON_0 bits 5 to 31 with CON_0 bits 0 to 4 driven by FTDI pins as desired.

This is one way of doing it:

module test2 (  CLOCK_50B, CON_0, FT_ADB0, FT_ADB1, FT_ADB2, FT_ADB3, FT_ADB4);

// Basic clocks
input  CLOCK_50B;

// CON_0 parallel ports
inout  [31:0]  CON_0;

// FT2332.. used for JTAG !
input  FT_ADB0; //TCK
input  FT_ADB1; //TDI
output FT_ADB2; //TDO
input  FT_ADB3; //TMS
input  FT_ADB4; //NRESET 

// NIOS mapping signal
wire   [31:0]   CON_0_nios; 

//CON_0 FTDI Assignments
assign CON_0[2] = (1) ? FT_ADB0 : 1'bz; //TCK
assign CON_0[0] = (1) ? FT_ADB1 : 1'bz; //TDI
assign FT_ADB2 = CON_0[1]; //TDO output from DUT drives FTDI
assign CON_0[3] = (1) ? FT_ADB3 : 1'bz; //TMS
assign CON_0[4] = 1'bz;

//CON_0 NIOS Assignments
assign CON_0[31:5] = CON_0_nios[31:5]; 

//CON_0_nios Inputs - not required as covered by port mapping
//assign CON_0_nios[31:0] = CON_0[31:0];

// Instantiate the Nios II system module generated by the Qsys tool:
nios2 u0 (
    .clk_clk       (CLOCK_50B),       //  clk.clk
    .CON_0_export  (CON_0_nios)       //  CON_0.in_port
);