# Bump in gain at high frequencies

I have designed an Op Amp inverting buffer (gain is 504/600 actually less than 1) stage. This is the schematic:

I seem to have a bump in gain at high frequencies, This is the ac response plot for out2:

Could you help me arrest this issue? having this would mean that my circuit is would amplify high frequency noise. Thanks!

• Each of your gain stages has a gain of around 20. Given the gain bandwidth product of 1.6GHz for the LT6200-10, you have an effective bandwidth of 66MHz for each stage. Looks to me like that falls right where the "bump" is. Too much gain and trying for too much bandwidth? – JRE Jun 1 '17 at 19:23
• What are you trying to do with that thing? – JRE Jun 1 '17 at 19:24
• Invert and Buffer the signal, I can't avoid the R6 1000 ohm resistor. As with 300 K source impedance, I will get hit on the bandwidth if I just use an inverting buffer. – Ash Jun 1 '17 at 19:43
• You say you built it - did you actually build it and if so what was your layout like? – Andy aka Jun 1 '17 at 20:59
• I meant designed it, not done layout yet. Sorry! – Ash Jun 1 '17 at 21:05

The "danger" with any non-inverting op-amp stage (your final stage) is that the op-amp's parasitic input capacitance to ground can rapidly increase the stage's gain at higher frequencies.

You thought you had a "straight" 300 ohm resistor to what is effectively 0 volts but, it is in fact, paralleled with the 4.2 pF of the input stage. Add to this a pico farad from the resistors and layout and suddenly, at about 100 MHz, you have a large peak in the frequency response.

Do the math - 300 ohm and 5.2 pF produces a cut-off frequency of 102 MHz and that will start to peak the gain at frequencies well below 100 MHz and the only thing that stops it rising up forever is the limited gain-bandwidth-product of the op-amp.

The first stage looks OK but I would also be concerned about the self-resonance of the 1 uF capacitors used. Look at this: -

As you can see, a lot of these capacitors turn inductive well-below your top operating frequency. This may make things worse (or better) but, the bottom line is that you should choose capacitors that don't become inductive at too low a frequency or you might open a can of worms.

Lack of decouplers on power pins of the op-amp is also a big worry and this will certainly cause problems at the sort of frequencies you are expecting.

If all you have done is a simulation then see if any peaking occurs in the first stage and also try feeding the 2nd stage directly with a signal to see if, as I believe, the peaking arises mainly here.