# Why does my ADS simulation provide no gain?

I am utilizing the following spice model for a BS170 MOSFET:

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*Zetex BS170P Spice Model v1.1 Last Revised 3/5/00

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.SUBCKT BS170P 3 4 5

• D G S

M1 3 2 5 5 N3306M

RG 4 2 270

RL 3 5 1.2E8

C1 2 5 28E-12

C2 3 2 3E-12

D1 5 3 N3306D

*

.MODEL N3306M NMOS VTO=1.824 RS=1.572 RD=1.436 IS=1E-15 KP=.1233

+CBD=35E-12 PB=1

.MODEL N3306D D IS=5E-12 RS=.768

.ENDS BS170P

15V, 120Ohm drain resistor, 0.25V input sine, and transient simulation. Bias at 2.5v

I have tried adjusting all the values, with and without the capacitor and so forth. If the DC bias is increased current starts flowing in the FET which decreases the Vout as expected, but at no point does it provide any AC gain.

The DC block, and the AC are outputting as expected. I am not sure how to troubleshoot any further. I am new to ADS so I might be missing something obvious. The parameters for gain are in the model. I did verify it has a transconductance parameter. This MOSFET is a very quick one so 1MHz should be no problem for it. I have an actual working model of it at 14MHz, too.

This has been solved by adding an inductor to the Vbias(gate)

• Double check that all nodes are properly connected. Sometimes in ADS it appears as if they are, when indeed they are not. – circuitpatrol Jun 2 '17 at 17:59
• Any reason you don't have a feed inductor between the bias source and the gate? Notice that there's no swing on Vgate... – Shamtam Jun 2 '17 at 18:04
• Shamtam, You should post that as an answer. An ideal voltage source at the gate shorts out the AC signal. – The Photon Jun 2 '17 at 18:22
• You are correct! That fixed it. Can you go into more depth on how/why that is shorting out the gate? – SubZero Jun 2 '17 at 18:37

By placing an ideal DC source at the gate of the FET, you're shorting the AC signal directly to ground. To answer your question in the comments (why is it shorting out the gate?), think about the gate of the FET as an equivalent impedance in parallel with your ideal DC source. The equivalent impedance of the ideal DC source is $0\Omega$ (think of Thévenin's theorem), whereas the equivalent impedance of the gate of the FET is considerably larger. As such, you've got a very low-impedance path to ground, so after passing through the feed capacitor, will mostly travel through the DC source to ground.