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For a S-R latch made of NAND gates, what happens when the latch is just powered and both the inputs of the latch are provided with logic level 1 simultaneously. What output do we get? Do the outputs remain constant or keep on changing?

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  • \$\begingroup\$ VDD noise and Boltzmann noise will tilt the decision. \$\endgroup\$ – analogsystemsrf Jun 4 '17 at 0:23
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In principle, yes, the two can form an oscillator. However, any mismatch in propagation delay (no matter how small) will cause the oscillation to die out. In any practical circuit this will happen almost instantaneously.

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Outputs are invalid below Vdd specs but you would expect both outputs to go high before it becomes valid. But then removing one input inactive low, after may be a race condition that is unpredictable.

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