I'm using an Altera Cyclone V DE1-SoC for an image processing project and to be able to do the "processing" on the FPGA, I thought I probably needed to store the image data on the FPGA first. So I went ahead and converted a sample image I want to use to a .mif file and used the Memory Compiler megafunction (RAM:1-PORT option). I chose the .mif file I created and made sure the number of words and bit widths match. Everything seems to have worked fine so far but... how do I actually use this data now? The .mif file contains the tone values of a 240x320 grayscale image and I need to go through these values one by one to apply Sobel edge detection. I did this using MATLAB without any built-in functions so I think I'll be able to write the necessary code in Verilog as well, just need to access the data. I'm pretty new to FPGA stuff so I'm sorry if this has a very simple answer.

(Also, if there are any methods that are more straightforward than initializing memory, please suggest them. I may be overcomplicating things unnecessarily but am not sure.)

Any help is appreciated! Thanks in advance.

  • \$\begingroup\$ Sorry if I'm wrong, but it reads to me like you're confusing an FPGA with a microprocessor. You do understand that you design a digital logic circuit for an FPGA - you don't 'write a programme' in Verilog/VHDL? Your FPGA is a giant pile of flip-flops, AND gates, OR gates, XOR gates, inverters and tiny RAMs all spread out on a table like Lego bricks? Let us know because it's paramount that you get that before we can answer much. \$\endgroup\$ – TonyM Jun 4 '17 at 9:53
  • \$\begingroup\$ Of course I know that, I've used this FPGA before, with schematics/block diagrams and also with Verilog. I know about logic design as well. I know the most basics of how an FPGA works also. What I meant was not a "program" in a software kind of way. But the FPGA will be manipulating an image turned into a simple array and for that it will use what I've provided it using Verilog. I don't think there's anything I'm assuming wrong about that part since I've done similar things before. \$\endgroup\$ – Volkan Mutlu Jun 4 '17 at 12:01
  • \$\begingroup\$ Oh good, this should be easy for you from what you say. First then, why have you loaded your image in by initial values during configuration - is it the only image you'll ever process? Otherwise you need an image input to RAM loading circuit and can throw away the initial values stuff. Secondly, the 'next bit' you're asking for is your entire design. Are you planning to design that yourself or will you pull in existing IP? Take a look on www.opencores.org, that might have some of what you want. \$\endgroup\$ – TonyM Jun 4 '17 at 12:09
  • \$\begingroup\$ Well, since this is like an assignment, there will be a test image that my system should be able to deal with and then I won't be developing this any further so I thought initializing the memory with one image should be enough for me. Of course it would be better if I could load new images on the fly but as I said, I've never used any memory blocks on the FPGA so I don't really know my way around them. Also, I will be designing this myself of course but I will check out the link you've provided, maybe it will give me some insight. Thanks! \$\endgroup\$ – Volkan Mutlu Jun 4 '17 at 12:21
  • \$\begingroup\$ This is confusing me - your question said you were new to FPGA design, your comments say how you know loads already 'of course'. If it's assignment, you can't use IP obviously and if you copy IP off opencores, your lecturer will probably spot it. It looks fairly complicated, you've got a lot of work in front of you. Anyway, I'll leave you to it and good luck with the homework. \$\endgroup\$ – TonyM Jun 4 '17 at 12:27

Two things:

  • there're Altera documents on embedded RAM describing how you access the RAM - for read and write; in your image processing circuit you will need state machine which would track address needed to be read, and waited for specific time to capture data outputted by the RAM;
  • it seems that you are currently hard-coding the data into the FPGA RAM (and RAM will be initialized with this data image after FPGA configuration). If you will develop your applications further when image can be loaded "outside" of the FPGA, I recommend you considering using 2-port RAM - one port is used for loading image (and connected to one state machine), and another port is used for processing the image (and connected to another state machine).

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