Gate delay of carry out C and sum S in ripple carry adder

Question

How to find the gate delay of carry out $C_{n}$ and sum $S_{n}$ in ripple carry adder?

I encountered this doubt while going through the book by Carl Hamacher.

It is written as:

Using the implementation indicated in figure (I have attached), $C_{n−1}$ is available in $2(n − 1)$ gate delays, and $S_{n−1}$ is correct one $XOR\,\,$ gate delay later. The final carry-out, $C_{n}$, is available after $2n$ gate delays.

I am completely stuck, how gate delay of carry out $C_{n}$ and $S_{n}$ is $2{n}$ despite carry is using total of 4 gates ans sum only 1 gate?

• Looking at it quick he appears to mean 2 gate delays times n stages (n is however many bits wide are being added). The AND, OR, and XOR gates only depict 1 bit adder, but block (FA) is a multiple bit adder. – Entrepreneur Jun 5 '17 at 16:18
• @Entrepreneur let it be $n$ bit adder consisting of obviously $n$ block.My question is that each block will take $1$gate delay ,then it must be total of $n$ delay ,how $2n$ is coming? – laura Jun 5 '17 at 16:21
• I am looking at the 3 AND gates feeding the OR gate. A carry-in (Ci) enters an AND gate then passes from the AND gate output through the OR (2 gates total traversed) before the Ci+1 output propagates to the next stage. – Entrepreneur Jun 5 '17 at 16:26
• okk,i too assumed the same but got confused in case of sum .why in case of sum , $2n$ gatedelay is used ?it is using a single $3$ input XOR gate.shouldn't be it $n$? – laura Jun 5 '17 at 16:29
• Each stage has two functions. 1) The XOR creates the new value of the output bit for the current stage bit result. 2) The AND-OR group creates the carry-out to the next stage. All of the carry bits must ripple from the lowest to highest stage to have a complete addition (like adding 1 to 99999 changes all higher digits). So the carry logic (can) delay the guaranteed result. – Entrepreneur Jun 5 '17 at 16:36

The figure on the right of your image is the carry of one bit position. Given a wordlength of $n$ bits and position $i$, the carry $c_{i+1}$ goes to the exact same circuit, just with inputs $x_{i+1}$, $y_{i+1}$ and $c_{i+1}$. So to calculate the carry of the total summation $c_{n+1}$ the signal takes $2 \cdot t_{Gate-Delay}$ times the number of bits: $2 \cdot n \cdot t_{Gate-Delay}$
Since the sum $s_i$ is calculated using two $XOR$-Gates it needs $2 \cdot t_{Gate-Delay}$ as cascading $XOR$-Gates is done by put them one ofter another, so calculating $s_n$ also takes $2 \cdot n \cdot t_{Gate-Delay}$.