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I was just wondering why do 4T-SRAM cell designs always have extremely high resistance (~GΩ). Is it because of the constant static power consumption?

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    \$\begingroup\$ The higher the resistance the lower the static power in pullup/pulldown resistors. There's a practical upper limit, because Johnson-Nyquist thermal noise increases with resistance, so you can't just use a petaohm resistor (which would be essentially the same as leaving it floating), but in general you want the highest-valued pullup/pulldown resistors possible. The exception is when dealing with MOSFETs, as the pullup/pulldown resistor is responsible for charging/discharging the gate capacitor, leading to significant speed reduction with high resistance. This isn't as big a problem with BJTs. \$\endgroup\$ – Hearth Jun 5 '17 at 17:32
  • \$\begingroup\$ Yes, and since they operate the same way as 6T Sram, the memory cell only drives the bit line low, the interface circuitry precharges the bus for a read. \$\endgroup\$ – sstobbe Jun 5 '17 at 17:33
  • \$\begingroup\$ @Felthry your comment should almost definitely be an answer. \$\endgroup\$ – Marcus Müller Jun 5 '17 at 17:38
  • \$\begingroup\$ I'll make it into one. Need to make things a bit clearer though, was trying to fit that into the character limit. \$\endgroup\$ – Hearth Jun 5 '17 at 18:34
  • \$\begingroup\$ thanks for the comments. I will reply on the answer itself \$\endgroup\$ – himura Jun 5 '17 at 19:30
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The higher the resistance the lower the static power in pullup/pulldown resistors. There's a practical upper limit, because Johnson-Nyquist thermal noise increases with resistance, so you can't just use a ridiculously high, say petaohm, resistor (which would be essentially the same as leaving it floating), but in general you want the highest-valued pullup/pulldown resistors possible. The exception is when dealing with MOSFETs, as the pullup/pulldown resistor is responsible for charging/discharging the gate capacitor, leading to significant speed reduction with high resistance. This isn't as big a problem with BJTs, though there is still somewhat of an effect.

FETs for high-speed applications, incidentally, are often push-pull driven to eliminate this exact problem. In this configuration, no pullup or pulldown resistors are used, and transistors are used to drive the line both high and low. This gives a dynamic impedance to both Vdd and Vss, so you can get all the benefits of a high pullup/pulldown resistor with none of the drawbacks.

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  • \$\begingroup\$ Thanks! I get it now. I just wanted to ask if you have any references for speeds/delays of 4T SRAM (since high resistance is bad for MOSFET but not so much for BJT). Do you have an idea how BJT and MOSFET based memories speeds are compared? \$\endgroup\$ – himura Jun 5 '17 at 19:33
  • \$\begingroup\$ Also, I would assume there's an area disadvantage with large resistors. \$\endgroup\$ – himura Jun 5 '17 at 19:36
  • \$\begingroup\$ Unfortunately, when it comes to SRAM, this is about as far as my knowledge goes. Large resistors are not necessarily larger in area, though. You can increase resistance by making a thinner path for the current, after all. \$\endgroup\$ – Hearth Jun 6 '17 at 2:15
  • \$\begingroup\$ That is true. It depends on the process. Thank you so much for this insight! \$\endgroup\$ – himura Jun 6 '17 at 10:49

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