If it's for Interrupt Service Routine (ISR) in which microprocessor pushes the content of program Counter(PC) to stack and then loads the Vector address in PC and starts executing the ISR stored in this vector address then what if the ISR needs more address locations. Will it overwrite the next interrupt's vector address? In fact for RST 4, TRAP(RST 4.5), RST 5, RST 5.5, RST6, RST 6.5, RST 7, RST 7.5 chain there's only 4 locations for ISR.
It makes this piece of address-translating circuitry easier to implement if the vectored-to addresses are a power of two apart. That was very important in this gate-starved design of 1974-odd.
The 8 bytes is long enough for a 3-byte JumP instruction to an ISR, a RET/RETI for unused ReSTarts or a brief handler routine. And its short enough that's its only committing 64 bytes of precious program memory if you're using all of the restarts, or running programs like an OS does, where you can't risk not having a handler for each RST. That's all said from the 1974 perspective of its design.
This was adopted into the Z80, which was a superset of the 8080 architecture and instruction set. The ZX Spectrum used the Z80 and its ROM listing shows how several of the 8-byte RST service routines contained part or all of a routine, not just JPs.