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I recently came across the Bit-banding feature on Cortex-M4 core and how it provides a solution to avoid race-conditions while toggling bits of registers. The M4 also has a dedicated BSRR register for performing atomic bit manipulation on the GPIO ports,I understand that using this makes the application thread-safe

Is there any downside to this approach compared to the generally used Read-Modify-Write method of toggling GPIO pins.If not, then why are GPIO_ODR registers provided for the cortex-m cores, why not use only the BSRR register for GPIO pin access.

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  • \$\begingroup\$ Take this case: toggling 8 pins(can be a port altogether) at the same time? Which is faster? \$\endgroup\$ – ammar.cma Jun 7 '17 at 10:37
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    \$\begingroup\$ @ammar.cma the BSRR/BRR can change up to 16 bits at a time if they are in the same port. But what these registers can't permit is transferring arbitrary data with an efficient fixed instruction. \$\endgroup\$ – Chris Stratton Oct 18 '17 at 6:41
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You assume that all operations on IO ports are at bit level. I wrote an external LCD interface a while ago that used Px0..Px7 for the data interface, and Px8 for the write control. This allowed me to directly stream a pixel (16-bit colour) to the display using a sequence of four GPIO_ODR writes. If I had used BSRR I would have had to translate the raw pixel data into bit masks for that register. This would have slowed things down significantly.

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You didn't specify the particular MCU in question, but the BSRR register is specific to ST Micro Cortex-M parts.

The BSRR register provides similar functionality to the bit-banding feature that is part of the Cortex-M architecture with regards to atomic operation.

As for whether bit-banding has a downside compared with doing read-modify-write, the main drawback is that they can only manipulate one bit at a time.

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    \$\begingroup\$ Note that unlike address-based bit banding, the BSRR and BRR do permit multi-bit operations, as they operate with bitmasks. \$\endgroup\$ – Chris Stratton Oct 18 '17 at 6:38
  • \$\begingroup\$ The GPIO ports that Arm licenses with the Cortex-M have a mask built into the port address, so you can do an atomic write of the port bits with a single operation. The only vendor that I'm aware of that use the Arm GPIO design is TI, although NXP does it in a similar way. Energy Micro/Silabs has ports with set/clear registers. \$\endgroup\$ – Robert Sexton Oct 19 '17 at 4:42

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