Just a couple of assumptions before I start as this is a theoretical question

  • All signals are <1MHz digital signals
  • All signals are single ended, no differential pairs
  • The 3 power lines are +5V, -5V and 12V
  • The ribbon cable is unshielded
  • The ribbon cable is inside a system with various other wiring looms carrying voltages/signals

What is the best placement for signal, power and ground lines within a ribbon cable with regards to EMI.

I have drawn up the two possibilities I could think of which are:

  1. Interleaving ground lines between each signal/power line
  2. Using the ground lines to create a barrier between the power and signal lines

enter image description here

Is one of these a better practice than the other or is there an even better solution which I didn't think of?

  • 11
    \$\begingroup\$ (1) is far better, for signal integrity and EMI. \$\endgroup\$
    – Neil_UK
    Jun 7 '17 at 11:38
  • 1
    \$\begingroup\$ How long is the ribbon cable? What type of digital signals (CMOS, TTL, etc.)? \$\endgroup\$
    – Glenn W9IQ
    Jun 7 '17 at 12:41
  • 3
    \$\begingroup\$ SLOW DOWN YOUR EDGES; make the edges be 500 nanosecond edges out of R+C filters. Allow no 1nS or 10nS edges (or MCU ringing) on the cables. This means the various VDD wires must also be heavily filtered BEFORE entering the cable. \$\endgroup\$ Jun 7 '17 at 12:49
  • \$\begingroup\$ Just FYI, there is such thing as twisted-pair ribbon cable, though it's less common than flat ribbon cable. Has flat areas at intervals for IDC connector mounting. \$\endgroup\$
    – MarkU
    Jun 7 '17 at 20:46
  • \$\begingroup\$ Plan on using Schmitt-triggered buffers to receive the signals, as this helps avoid problems with ringing/line termonation effects. \$\endgroup\$
    – MarkU
    Jun 7 '17 at 20:49

Interspersed signals with grounds or rails is best for EMI and crosstalk purposes, so your option 1 is better here.

However, in your example you have seven ground wires and only one wire for each power rail. Assuming your signals are mostly logic level, i.e. 5V rail, it would be preferable to reduce the ground lines to four and add three more 5V lines. This will help balance the return current paths for both signal levels.


simulate this circuit – Schematic created using CircuitLab

Note, with your current setup, when the signal is high the return current is through the shared grounds, when it is low, the return current is through the single wire. Add more signals and the single wire must share all those signals and noise will be seven times more significant on the rail wire.

If the other rails are driving significant currents you should also increase their counts appropriately to try and balance the currents over the available wires.

In addition, as analogsystemsrf mentioned, if the cable is of any appreciable length, it is prudent to slow down the edges of logic signals passed along the cable. Your signals may be low frequencies, but those digital edges are not.

  • 1
    \$\begingroup\$ Assuming that the power supplies on both boards are adequately bypassed, power and ground lines are completely equivalent in terms of "return currents". There is no need to balance the number of power lines with the number of grounds. Instead, anything you can do to reduce the overall impedance of the ground connection between the two boards will be a benefit. \$\endgroup\$
    – Dave Tweed
    Jun 7 '17 at 14:03
  • \$\begingroup\$ @DaveTweed not so.. If you have all signals low, and are powering the peripheral through the cable, the entire return current will have to pass through the single rail wire. Though I agree, "anything you can do to reduce the overall impedance of the ground connection between the two boards will be a benefit" \$\endgroup\$
    – Trevor_G
    Jun 7 '17 at 14:06
  • 1
    \$\begingroup\$ Are you saying that the DC current of the signal lines is a significant fraction of the total power being consumed by the board? That would be a very unusual situation, and is certainly not indicated in the question. I was talking about transient return currents, which are the usual concern with regard to EMC. \$\endgroup\$
    – Dave Tweed
    Jun 7 '17 at 14:14
  • 1
    \$\begingroup\$ And again, in your new diagrams, you have neglected the bypass capacitors on both ends of the connection. -1 from me. The only valid part of your answer is the very first paragraph. \$\endgroup\$
    – Dave Tweed
    Jun 7 '17 at 14:46
  • 1
    \$\begingroup\$ @Trevor I think what Dave is pressing on is that if the bypass caps are handled correctly on both ends, and if you included them on the schematic, then it would be explicit how transients would be bypassed to the Vcc rail through them on both sides (which means the need for balancing actual Vcc wiring in the cable itself is already 'covered' by the bypassing at src and dst.) And if you agree with him about the bypass, then I think he's saying you lose the whole discussion about needing to balance the wiring between gnd and Vcc. It disappears and becomes a non-issue (or pointless.) \$\endgroup\$
    – jonk
    Jun 7 '17 at 15:58

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.