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Hi I have been trying to create a custom Brushless DC motor driver circuit using P type and N type transistors (known as H bridge).

This is the circuit I designed and prototyped on the breadboard. Im using and gates to control the PWM of the H bridge.

Circuit Diagram Here

  • Im using IRFZ48N (P channel) and IRF4905 (N channel) as mosfets
  • Im feeding it with 24V DC.
  • Im using an Arduino mega to feed it with 62khz signal and gate states. The software makes sure that pin going low comes before pin going High (so that it doesn't conduct both N and P at same time.

The IRFZ48N mosfet in the middle down sequence (Next to the Q3) gets overheated

Currently I dont have any oscilloscope so can't do any measurements wave wise, but I have couple of multimeters with 2 point presicion if that helps to measure.

The circuit seems right to me even though it gets heated. Any help would be appriciated

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    \$\begingroup\$ IRFZ48N is N channel, IRF4905 is P channel. Caution: You are exceeding Vgs max for IRF4905 (20V) (and probably also for IRFZ48N). You really should use decent gate-drivers for this, passive turn-off may be your heat problem. \$\endgroup\$
    – Tut
    Jun 7, 2017 at 12:21
  • \$\begingroup\$ could you explain me what did you mean by "passive turn off" Im havent mastered english terms of electricity yet. Thanks For the answer :) \$\endgroup\$
    – xDeathwing
    Jun 7, 2017 at 12:34
  • \$\begingroup\$ By "passive", I am referring to your 10K resistors which cause your MOSFETs to turn-off too slowly; and you don't need (or want) 24V from gate to source to turn-on your MOSFETs. Read the datasheets. \$\endgroup\$
    – Tut
    Jun 7, 2017 at 12:43
  • \$\begingroup\$ You should also replace your flyback diodes with Schottky diodes. \$\endgroup\$
    – Tut
    Jun 7, 2017 at 15:02
  • \$\begingroup\$ Constructing this on a breadboard is dubious, but it does mean you could swap the overheating FET with one of its siblings and see if the problem moves with it. You may well have blown the gate oxide on that one; design or implementation flaws may mean the others will soon be damaged as well. \$\endgroup\$
    – Chris Stratton
    Jun 7, 2017 at 15:30

1 Answer 1

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You need a GROUND PLANE. You need a POWER PLANE.

You need fast time-constants, and 10Kohm+10nF Cgate is 100,000 nanoseconds Tau; thus your gate drive is underpowered.

You need large Cbypassing between GND and Power planes, able to support one amp load for 0.5 * 1/60 Hz period, with only 0.1volt sag. Using Q = C * V, differentiating to become I = C * dV/dT, and re-arranging to show C = I * T / V, we compute Cminimum_bypass = 1amp / 0.08 Second * 0.1volt = 8,000 uF.

Because that Cbypass must support the entire 1amp load (assumed) between recharge cycles, you need to design your VDD filtering to be Rectifier--1,000uF and 1 volt ripple --- linear regulator (lotta HEAT here) with 8,000uF (plus its large lead inductance) in parallel with 10uF ceramic between the VDD and GND planes using 5 vias at each end of the 10uF to achieve LOW inductance.

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