# What is the structural difference between a high-drive and a low-drive cell?

I've come across IC's that are labeled high-drive and low drive. I know that a high-drive IC has a higher intrinsic propagation delay but isn't as steep as a low-drive IC in function of the load to drive.

If I were to design both a high-drive and a low-drive NOT-gate (or any other logic gate), what would the difference be between the designs?

In the picture the dotted line is the high-drive cell and the full line is the low-drive cell.

• what did you not understand in my answer? The more technical answers are in my link – Tony Stewart Sunnyskyguy EE75 Jun 17 '17 at 0:15

The short answer is the size of the transistors. The wider the gate is, the lower the Rdson of the FET is - but the wider gate has increased gate capacitance, so it presents a larger load to its input and takes longer to switch.

• What would the long answer be? – Casper Vranken Jun 10 '17 at 18:09
• The long anwser would be to do the math or simulation of the said implementations in order to sustain this "simple" explication. For a "simple" NOT-gate, one difference is at least the size of the output transistor. There may also be some extra transistors as in a Darlington setup in order to provide enough drive to this output transistor. – le_top Jun 12 '17 at 0:55
• Wherever you got this graph assumed a family of chips with lower Rdson Nch for Low side SWitch (generally true for same size) and thus higher current drive into C load and lower Ton time vs C however the slope indicates dt/dC steeper slope for some odd reason. where Ic=CdV/dt + VdC/dt and the latter is normally 0 in caps, but is not zero in FETs and rises with 1/RdsOn so dt=(CdV+VdC)RdsOn/Vds may be simplified to select appropriate FETs with low RdsOnCoss (Figure of Merit) that contribute to propagation and rise time delay – Tony Stewart Sunnyskyguy EE75 Jun 12 '17 at 5:02

THis graph shows a lower $t_P$ propagation delay for the steeper sloped curve at $C_L=0$ and slower rising product with load capacitance such that at some crossover point the two devices have equivalent $t_P$.

The definition of propagation delay depends on the next stage such as Rail to Vdd/2 or rail to rail 10~90% the more traditional pproach for a linear step pulse. In a linear transmission line surrounded by a linear dielectric and possible magnetic component the prop. delay is defined as ;

$t_P=3.333 \sqrt{{\mu _r}{\epsilon _r}}$ ns/m
This means the speed of light or waves reduces by the square root of the product of (permitivity * permeability ) relative to a vacuum.

I will say now that the higher flatter slope is a "bigger" MOSFET switch ( with more internal capacitance) and the lower steeper slope is a "smaller" MOSFET part ( with higher RdsOn ) and then explain why.

We know both internal and external load capacitances affect rise time $I_c=CdV/dt$ according to the gate driver & output driver current , thus both will contribute to output propagation delay.

We know that charge flow dQ/dt=I, current and capacitance is the change of charge size with voltage C=dQ/dV thus we get the familiar I=CdV/dt or rearranging slew rate which affects delay from 10 to 90% of voltage

$dV/dt=I/C$ capacitance voltage slew rate is current limit by I, or in other words;

$dt=CdV/I$ the propagation delay with voltage rise depends on the step size of the voltage dV and the current driver to load C, where the current , Id

$I_d=(V{ss}-V{dd})/R_{dsOn}=I_C=C_LdV/dt$ thus

additional prop delay includes rise time, so re-arranging again

$dt=\dfrac{R_{dsOn}C_LdV}{V_{ss}-V_{dd}} \text{ but } dV=(V_{ss}−V_{dd})$ which cancels out thus... $\ dt= {R_{dsOn}C_L}$ the rise time which adds to prop delay $t_P$.

What ends up happening is the source and gate resistance limits gate drive current contributes some prop delay so a "bigger" switch is not expected to be faster due to gate drive prop delays, but then the lower drain to source resistance, RdsOn boosts the current during switching so load capacitance has less effect than the smaller device with higher RdsOn.

But since device RdsOn is inverse to Coss in a given family and voltage rating and current rating for different values , it ends up that T from output switching capacitance, Cosshas a Figure of Merit (FoM) of RdsOn*Coss=T product which is fairly constant for the same family of geometry voltage and other factors. So when external capacitance is smaller the Coss, it makes little difference in prop delay, but if Coss is much smaller thanC load it makes a big difference and prop delay rises faster with load C as shown in the graph.

For the more advanced student here are lecture slide shows on how device internal capacitance is defined, controlled and calculated, but are not necessary to understand this question.