# Why aren't cascaded NOT gates used as frequently as flipflops?

simulate this circuit – Schematic created using CircuitLab

I am going through Digital Electronics course and came across Flip Flops. As the cascaded NOT gates basically do the same functioning of storing the bits as Flip Flops do(just connect output of second NOT gate to input of first NOT gate), and that too with use of only two gates(for flip flop there are at least two NOR or NAND coupled, plus two AND gates for combining clock), why aren't they used as much as flip flops are used?

• Not getting what you mean, edit your question and use the schematic drawing tool to draw examples of what you mean. Draw a flip-flop using NOR gates as you propose and see how that works out. Commented Jun 8, 2017 at 8:17
• Also your title makes no sense, an inverted NOT gate is a buffer which cannot be used as a flip-flop. Commented Jun 8, 2017 at 8:24
• I am sorry I wrote 'inverted' for 'cascaded'. Commented Jun 8, 2017 at 8:28
• What they said. | Plus: Your cct needs extra components to make it practical - the input must be able to override NOT2 when desired but then allow NOT2 to dominate. This can be done eg by adding diodes at the input (one for each input state) and a resistor from NOT2 out to NOT 1 in. Then you may need clocking. And the gates need at a minimum 2 transistors to implement (in CMOS) arguably one in RTL with vast care). Overall its less flexible and no cheaper. || All that said - I have used this in some applications in the past :-). ... Commented Apr 27, 2020 at 2:32
• ... Using a hex CMOS Schmitt trigger eg CD40106 this is a very useful circuit. See eg here and here Commented Apr 27, 2020 at 2:32

This circuit:

simulate this circuit – Schematic created using CircuitLab

is inconvenient to use as a memory element. Because, how do you change its state ? If the output is 0 and I want to load a 1 it will be a contest between me feeding the 1 at the input and the output wanting to keep it 0.

If I'd use a very strong driver to drive the input it would always "win" but how would that store the bit ? It would not, the output of this circuit would simply follow the input, it would behave as a buffer.

A solution is to use a Tri-state output to drive this circuit, then in the "open" state of the strong driver (which drives the input) the bit would be remembered.

Still a stronger driver is needed and this is inefficient and there's a better way. Make the output of NOT2 also tri-state. Then when the memory needs to be written, make the output of NOT2 highZ and apply data at the input. Of course again the input must be driven with a tri-state output also but it does not have to be "strong" as NOT2's output will do nothing when the data is written.

In practice this kind of circuit (but with the tri-state outputs) is used only inside flip flops. Something like this:

Sorry that this is a blurry picture, it's the best I could find. I have better ones but I cannot share those (they are commercial designs).

The 4 transistors on top of each other (2 PMOS + 2 NMOS) are basically inverters (NOT gates) with a tri-state (high Z) option. Note how the 2 stacks of 4 transistors on the right side "bite eachother's tail" just like in your schematic. That is the memory cell !

Because connecting 2 outputs together is bad in the general case. your schematic requires that the input signal overrides the output signal in some way, but not all the time (to be able to use it as a latch). This means you can't use binary signals to control this latch. You need a third input state that says to output whatever is latched.

However you rarely need the pure SR latch. Most of the time you need the latch to be clocked (latch on clock edge) or be gated with an enable input. That requires extra logic.

Because 2 cascaded NOT gates has only part of the behaviour that a flip-flop has. It will store a state, but it has no means to set the state.

Flip-flops have a number of inputs for setting the output to the wanted state, usually a few from the many options of clocked or asynchronous set and reset, clock and data, or latch and data.