I have seen references to that feature here and here (pg 20) I can't quite get why it is useful. Since the memory controller selects the rank, wouldn't be the same if the address on the rank would have been the same as the bank/row/col selected by the memory controller?


Imagine the situation - you have perfect circuit diagram, which connects processor (CPU) to the RAM chip. A0 of processor goes to A0 of the memory chip, D0 of processor is connected to D0 of memory chip.

But when you start routing connections on the board, you see that your perfect circuit routes very badly, requires a lot of vias, conductor corners, long traces etc.

The principle that it does not matter how you physically route RAM array, what matters is that data written to specific location must be read from that same location, not another one.

Thus, generally, you can connect address and data pin groups of single or multiple RAM chips in any way which you see the best for board routing to have shortest tracks and minimal number of vias.

But there're issues:

  1. Modern chips, even RAM chips, may be so clever that they need to be programmed or commanded through specific pins - and this requires driving specific pins of the single or several chips (so that command goes properly). Thus, for these clever devices you can not just rewire everything as you want, you need to ensure that non-interchangeable pins stay on their designated lines;
  2. Refresh addressing - worth mentioning, but should not be the issue for modern SDRAM chips as they must have internal refresh mechanisms. However, if these mechanisms are not used, and array is refreshed by the controller, designer must ensure array refresh is performed as required, and there're no locations left which may lose their contents without being refreshed within specific time frame;
  3. This rewiring will totally not work for pre-programmed ROM (PROM/EEPROM/flash) devices, because they are factory written in one order of address and data, and must be read with the same order (unless factory image is specially prepared with data bits and address lines reordered).

So that's why both sources you list state several pins as eligible for swapping, and some not eligible. Samsung's datasheet is the best describing it.

The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5,A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table ... Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.

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    \$\begingroup\$ Also flash chips typically receive commands/return status through the address and data lines so you have the same problem as mentioned in #1. \$\endgroup\$ – DoxyLover Jun 8 '17 at 22:42
  • \$\begingroup\$ The main thing that require address pins to be in a specific order on modern SDRAM I think is the load mode register command. \$\endgroup\$ – Yuhong Bao Jul 24 '17 at 19:59

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