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In one of the questions I am trying to resolve, I am given the Vbe waveform and I am told to draw "waveforms related to Q1". I am guessing that means the emitter voltage waveform - right?

The Vbe waveform: enter image description here

This is the buck converter circuit:

enter image description here

The Vbe waveform seems very vague to me. I cant understand what that horizontal plateau in the middle of the positive part signifies?

Update:

So since I am asked to draw the waveforms related to Q1, I added teh Collector and Emitter voltages on the same waveform. Am I right?

enter image description here

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Vge implies IGBT not NPN. THe mid plateau may be gate discharge thus gate current during the threshold of output conductance and the upper plateau when saturated BJT output. IGBT's have FET input and BJT output. The time period may be 10us for a half cycle of a 50KHz PWM rate. The input voltage slew rate is limited by (Rg+Rs)*Ciss. The output slew rate is limited by L with a hopefully low Q LPF.

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  • \$\begingroup\$ Thanks that helps a bit. So since I am asked to draw the waveforms related to Q1, I added teh Collector and Emitter voltages on the same waveform. Am I right? \$\endgroup\$
    – user1406716
    Commented Jun 10, 2017 at 3:33
  • \$\begingroup\$ Yes next examine Ie . when Ve rises starting at mid plateau so delta slope then step , examine change in Ve=LdI/dt and I rises with cap current Ic=CdV/dT. THe change in voltage is usually with parts chosen to make a small change for Vc in a half cycle so gain of SMPS regulator is not so high that it becomes noisy with ripple voltage for each cycle charging the cap with no load.(yet) \$\endgroup\$
    – D.A.S.
    Commented Jun 10, 2017 at 4:32

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