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I am building a 1-bit register using a DFF:

schematic

simulate this circuit – Schematic created using CircuitLab

The problem I have is that I think it should be saving whether D is high or low when the clock pulses and outputting that to Q. How do I go about doing that?

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  • \$\begingroup\$ R1 is going to be dissipating 0.25 W all the time - you probably don't want that to be happening. SW1 does nothing with the circuit as shown. Perhaps the circuit diagram did not come out as you intended and needs to be edited. \$\endgroup\$ – Andrew Morton Jun 10 '17 at 21:53
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I'm understanding your question to be asking: why can I only store a high bit, no matter where I switch SW2 to?

If I've got that right...

SW2 correctly puts 5 V onto D when switched on. But it leaves D floating (undriven) when SW2 is switched off. The input stage of some 5 V logic families will cause them to see a high on floating inputs.

Try connecting a pull-down resistor between the D pin and GND. A 10 K resistor is a good start but for LS you might need (say) 2K2.

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For bipolar TTL parts like the plain 74xx series, or 74LSxx, the inputs will appear High, unless pulled Low by a low resistance - under 500 Ohms should do. So, in your circuit, the D input will be high at all times.

Since inputs source significant current, it is common practice to use a pull-up resistor of 5K or so to +5V, with a switch from the input to Ground, to ensure that the input will really be recognized as Low when it should be.

For CMOS parts (74AC, 74HC), the inputs are high impedance and if left unconnected will float randomly between High and Low - they must be pulled up or down as required with a 5K or more resistor. This includes inputs on unused parts of the chip, like the second latch in the 74xx74 package.in your circuit

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