enter image description here

It seems obvious that the mirrored symmetry in current between IR2 and IG must be displaying the same phenomena, but I admit that while learning LTSpice and running simulations for a future circuit.

It is confusing as to why it is displaying a \$3\mu A\$ spike for the gate readout, and a negative for the resistor. I understand that there is current needed to achieve gate charge for threshold, but why is R2 negative?

The explanation may be simple, but it's been a long day and I'd like to understand what's happening.

  • 3
    \$\begingroup\$ Maybe if you rotate R2 180 degrees the current will show up as positive? \$\endgroup\$ – Dampmaskin Jun 12 '17 at 23:02
  • \$\begingroup\$ Well looks like it was that simple. I didn't know Spice had that requirement. Thank you @Dampmaskin. \$\endgroup\$ – Archaeus Jun 12 '17 at 23:44

IIRC, this is related to SPICE, in general: the elements have numbered pins. Where two pins are concerned, it is considered that the current flows into one pin, and goes out from the other.

This has to be known prior to simulation in order to correctly build up the matrix solver. This is why the currents may appear as opposite polarities in the same branch.

The solution is simple, as mentioned by @dampmaskin. For more than two pin elements, it is considered that the current goes in the pin, for all pins.


I think it's a model thing. The voltage on the gate slowly rises until the gate threshold voltage in your model is met, at which time the FET switches. When this happens, the drain is pulled down toward ground.

The gate-to-drain capacitance then drives the gate voltage more negative, but in the model, it only drives to until it hits the gate threshold voltage which acts as negative feedback, slowing the switching time of the FET until everything is balanced.

The model's rise time keeps the gate voltage at the gate threshold voltage until the FET is through switching, after which time the gate voltage is allowed to rise. Since the voltage at n003 continues to rise, and the gate voltage does not, the current flowing into n003 through R2 has to be negative.

You can verify this by putting a node between R2 and the gate and it should stay around VGS(TH) until the voltage on R3 gets pulled down.

  • \$\begingroup\$ Thank you for the reply. I dropped a node but the reading did not show that result. node3 and node4 to Gate were identical. Taking @dampmaskin simple 180 fix did reverse the process and showed identical current. If you feel strongly about your answer, I'll investigate further, but it seems as if it may have just been a simple reversed simulation component. \$\endgroup\$ – Archaeus Jun 12 '17 at 23:55

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.