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My textbook says this enter image description here

I get that the quiescent power dissipation is \$P_{DQ}=V_{CEQ}I_{CQ}\$. But, when a signal is present, the instantaneous Q point simply varies sinusoidally around the dc quiescent point. This means the instantaneous \$V_{CE}\$ and \$I_C\$ can go higher than \$V_{CEQ}\$ and \$I_{CQ}\$. I think this should cause some "additional" rms power \$P_{signal}\$ dissipated in the transistor; so shouldn't the total power be \$P_{DQ} + P_{signal}\$ ? I don't really get how \$P_{signal}\$ steals the power from \$P_{DQ}\$. Appreciate any help. Thanks!

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    \$\begingroup\$ In your assumption you change the operating (Q-) point with the input signal. But that is not how an operating point works ! The operating point remains fixed and the signal causes deviations from that point. Looking at it like that makes the book's statement true (for some amplifiers at least). Also, the instantaneous Vce and Ic can also be lower than the operating point. \$\endgroup\$ – Bimpelrekkie Jun 13 '17 at 6:35
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    \$\begingroup\$ Sure but that does not change the average operating point. The signal causes variations over the load line but the operating point stays in the middle. \$\endgroup\$ – Bimpelrekkie Jun 13 '17 at 6:40
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    \$\begingroup\$ No it does not, see Andy's answer below. The signal not only causes more power to be dissipated in the positive peaks but also less power to be dissipated in the negative peaks. And in a class A amplifier (like a simple one transistor common-emitter) this "extra power" part is compensated for by the "less power" part resulting in an average of zero. \$\endgroup\$ – Bimpelrekkie Jun 13 '17 at 6:45
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    \$\begingroup\$ Yes, for class A amplifiers that is the case. For class AB and B it is a different story, they draw extra power from the supply but only when needed (when driving a "heavy" load with a large signal). \$\endgroup\$ – Bimpelrekkie Jun 13 '17 at 6:56
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    \$\begingroup\$ The quiescent point being worst case is a bold statement... I would recommend reading up on output stage efficiencies as class-a into Restive load tops out at 25 % eff. \$\endgroup\$ – sstobbe Jun 13 '17 at 6:56
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For the BJT in Common-Emitter configuration the power dissipation in the BJT is always equal to:

$$P_D = I_C*V_{CE}+I_B*V_{V_{BE}} \approx I_C*V_{CE} $$

In Saturation when the BJT is fully-ON the \$V_{CE}\$ reach the lowest value and the collector current reach the maximum value. But overall the power dissipation is small. We have the same situation when BJT approaches cut-off. Hence the maximum power dissipation must lay somewhere between saturation and cut-off region in the active region.

Let us exam this circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

And let us plot Ic vs Vce and the power dissipation in the BJT

enter image description here

As you can see the worst case scenario is when:

\$ V_{CE} = \frac{Vcc}{2} \$ and \$ I_C = \frac{I_{Cmax}}{2}\$

Where \$ I_{Cmax} = \frac{Vcc}{R_L}\$

So finally we can find:

$$P_{Dmax} = \frac{Vcc}{2}*\frac{\frac{Vcc}{2}}{R_L} = \frac{Vcc^2}{4R_L} = \frac{20V^2}{4*500\Omega} = \frac{400}{2000} = 0.2W $$

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  • \$\begingroup\$ Looks really neat! Thank you :) I think you have something like this : $$i_c = -kv_{ce} + I_{csat}$$ $$p_{inst} = v_{ce}i_c = v_{ce}(-kv_{ce} + I_{csat}) = -k{v_{ce}}^2 + v_{ce}I_{csat}$$ Its a simple quadratic and the maximum value occurs somewhere between 'sat' and 'cutoff'. \$\endgroup\$ – Hiiii Jun 13 '17 at 14:00
  • \$\begingroup\$ Hey @G36 is there any reason why \$i_c\$ versus \$v_{ce}\$ should be linear (blue line) ? \$\endgroup\$ – Hiiii Jun 13 '17 at 14:01
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    \$\begingroup\$ The blue line is the load line for a given RL. And the resistor is a linear device. \$\endgroup\$ – G36 Jun 13 '17 at 14:09
  • \$\begingroup\$ My bad! gotcha xD \$\endgroup\$ – Hiiii Jun 13 '17 at 14:23
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From the perspective of a simple, theoretical class A amplifier, the power taken from the supply is voltage x current. If the current is a DC value with a sine wave superimposed on top (representing the current delivered to a load), providing the supply voltage remains constant, the average power into the amplifier remains unchanged from the quiescent DC case.

Mathematically it can be broken down into: -

Power = average[(DC voltage x DC current) + (DC voltage x AC current)]

The average of the 2nd term is of course zero.

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  • \$\begingroup\$ Ahh nice, that means "quiescent power" and the "average power with signal" dissipated in the transsitor are equal. But the textbook says the input signal is "decreasing" the power dissipated in the transistor ? @Andy aka \$\endgroup\$ – Hiiii Jun 13 '17 at 6:49
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    \$\begingroup\$ Actually it is when the amplifier is loaded and the load receives (signal) power. That power is not dissipated in the transistor anymore but dissipated in the load. For class A amps. total average power is constant. Without a load the power can go nowhere but into the transistor. When there is a load and a signal, part of the power goes into the load. \$\endgroup\$ – Bimpelrekkie Jun 13 '17 at 6:54
  • \$\begingroup\$ @Hiiii my answer has established that power taken from a DC supply is constant (for a constant supply voltage) therefore, if power is taken by the load, the power in the transistor(s) has to reduce. \$\endgroup\$ – Andy aka Jun 13 '17 at 7:05
  • \$\begingroup\$ Makes sense, thank you :) Let me see if I understand this : 1) With out load, the "average power" dissipated in the transistor is same as the "quiescent power", with or without the input signal. 2) Adding load decreases the power disipated in transistor ---- I believe the textbook is completely wrong when it says the power dissipated in the transistor is less when the "input signal" is present ? \$\endgroup\$ – Hiiii Jun 13 '17 at 7:10
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    \$\begingroup\$ @Hiiii I think what may be confusing you is the load being connected or not. For a simple black box class A amplifier, it can be assumed that the load is always connected BUT even though it is connected, it is wired in such a way that in quiescent conditions there is no power dissipated by the load. It may be capacitively connected so that there is no DC voltage present on the load for instance. So, when an input signal comes along, the average power taken from the power supply is the same but, because power is now sent to the load, there must be a power reduction in the transistor(s). \$\endgroup\$ – Andy aka Jun 13 '17 at 9:17
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Assume that the quiescent operating point is \$\small (V_{CEQ},\: I_{CQ})\$, so the quiescent power dissipated by the transistor is \$\small P_Q=V_{CEQ}I_{CQ} \$

Now, let the load-line be of slope, \$\small - \frac{1}{R}\$, and assume that the input signal to the base is a square wave that causes \$\small V_{CE}\$ to vary between \$\small (V_{CEQ}-\Delta) \$, and \$\small (V_{CEQ}+\Delta) \$, where \$\small \Delta\$ is the amplitude of the square wave superimposed on \$\small V_{CEQ}\$.

The corresponding collector currents will be \$\small \left (I_{CQ}+\frac{\Delta}{R}\right) \$, and \$\small \left (I_{CQ}-\frac{\Delta}{R}\right) \$, respectively (remember the negative slope of the load-line).

Hence the average power dissipated by the transistor over one complete cycle of the square wave will be: $$ P_{sq.wave}\small=\frac{1}{2}\left [\small \left (V_{CEQ}-\Delta\right) (\small I_{CQ}+\frac{\Delta}{R})+\small \left (V_{CEQ}+\Delta\right) \small (I_{CQ}-\frac{\Delta}{R})\right ]$$

giving: $$ P_{sq. wave}\small =V_{CEQ}I_{CQ}-\frac{\Delta^2}{R}= P_{Q}-\frac{\Delta^2}{R}$$

Therefore, less power than quiescent is dissipated by the transistor when a small signal is applied.

An input sinusoid will give a similar result, but requires integration to get the average power over one cycle, rather than the piecewise linear analysis required for a square wave. The result for a sinusoidal voltage of amplitude, \$\small \Delta\$, about the quiescent point is: $$ P_{sine}\small= P_{Q}-\frac{\Delta^2}{2R}= P_{Q}-\frac{\Delta_{rms}^2}{R}$$

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