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How can I make a two phase clock on a breadboard (i.e. no surface mount components) without using a microcontroller?

Phase 1:

   _     _
__| |___| |__

Phase 2:

  ___   ___
_|   |_|   |_

The exact duty cycle is not important.

Phase 1 must go low at least 50ns before phase 2 and go high at least 50ns after phase 2.

Ideally, the clock needs to be adjustable (via resistors, capacitors, etc.) between 1Hz and 100KHz.

I have been thinking about ANDing and ORing two 90 degree out of phase 50% duty cycle clocks - but I still need to generate those.

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  • 1
    \$\begingroup\$ Why don't you want to use a microcontroller? A micro is a good way of getting a variable clock (1-100000Hz range is going to be hard otherwise), and can easily provide the two overlapping clocks you want. You can probably do this with just one IC for about $1. \$\endgroup\$ – Jack B Jun 13 '17 at 12:53
  • \$\begingroup\$ @JackB I'm building a home-brew CPU and I don't want 99.999% of the computing power to be in the clock generator. \$\endgroup\$ – fadedbee Jun 13 '17 at 13:02
  • \$\begingroup\$ Please be aware that you need to be careful, and that means reading the data sheet closely. Your 60 nsec delay assumes a) a specific 50 pF load and b) a 10 volt power supply. Furthermore, this is a typical number, and is not guaranteed. \$\endgroup\$ – WhatRoughBeast Jun 13 '17 at 18:01
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You can do this using two 4:1 multiplexers and a frequency divider (a simple flip-flop will do).

Divide your input signal using a flip-flop to half the frequency. The run the original frequency and the divided frequency into the S1 and S0 inputs of a CD74HC253 multiplexer Datasheet.

This will output the voltage present at the inputs 1 to 4 at the output in serial order.

You can use these four inputs as a generic table and 'program' any four step sequences that you need. For your signals:

Apply these at the first multiplexer inputs:

1I0: low
1I1: high
1I2: low
1I3: low

And for your second sequence:

2I0: high
2I1: high
2I2: high
2I3: low

You'll get your two phase signal at the outputs 1Y and 2Y at half the clock frequency.

To compensate for the lower frequency, either run the circuit at twice your wanted frequency or use a PLL to double the frequency of an existing input clock.

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  • \$\begingroup\$ Running clock signals through the muxes is usually a bad idea, because race conditions can introduce glitches. It should work in this particular case though. \$\endgroup\$ – Dmitry Grigoryev Jun 13 '17 at 9:02
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Use a 2-bit binary counter (two D flip-flops), then use some simple combinational logic to generate the phase1/phase2 outputs. This could be individual AND / OR / NOT gates, or it could be a decoder such as 74__139.

There are four ways to map the counter state to the phase1/phase2 waveforms, you can choose whichever seems the easiest to implement. Remember to consider the initial state of the counter as well.

At 100kHz there shouldn't be any major issues with using solderless breadboard. Up around 10MHz solderless breadboard starts to reach its limits.

------|-------|------
a1 a0 |phase1 |phase2
------|-------|------
0  0  |0      |0
0  1  |0      |1
1  0  |1      |1
1  1  |0      |1
0  0  |0      |0
0  1  |0      |1
1  0  |1      |1
1  1  |0      |1

phase1 = a1 AND (NOT a0)
phase2 = a1 OR a0

------|-------|------
a1 a0 |phase1 |phase2
------|-------|------
0  1  |0      |0
1  0  |0      |1
1  1  |1      |1
0  0  |0      |1
0  1  |0      |0
1  0  |0      |1
1  1  |1      |1
0  0  |0      |1

phase1 = a1 AND a0
phase2 = a1 OR (NOT a0)

------|-------|------
a1 a0 |phase1 |phase2
------|-------|------
1  0  |0      |0
1  1  |0      |1
0  0  |1      |1
0  1  |0      |1
1  0  |0      |0
1  1  |0      |1
0  0  |1      |1
0  1  |0      |1

phase1 = a1 NOR a0
phase2 = a1 AND (NOT a0)

------|-------|------
a1 a0 |phase1 |phase2
------|-------|------
1  1  |0      |0
0  0  |0      |1
0  1  |1      |1
1  0  |0      |1
1  1  |0      |0
0  0  |0      |1
0  1  |1      |1
1  0  |0      |1

phase1 = (NOT a1) AND a0
phase2 = a1 NAND a0

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A CD4001BE dual NOR gate with a dual CD4011BE NAND gate would do the job.

They have a 60ns delay each.

Wired as:

schematic

simulate this circuit – Schematic created using CircuitLab

This will drive 74hcXXX logic correctly: Can original CD4xxx logic drive 74HCxxx logic?

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  • \$\begingroup\$ Hi, Chris. You've posted a question as an answer. SE doesn't work like a forum, answers float up and down depending on votes or user's sort order so it will cause some confusion. Edit your original question and delete this answer. There's a very easy-to-use schematic editor built in. \$\endgroup\$ – Transistor Jun 13 '17 at 15:55
  • \$\begingroup\$ I've amended the answer, so that it refers to question, rather than asking one. \$\endgroup\$ – fadedbee Apr 25 '18 at 12:29

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