# Help needed with verilog testbench

could anyone explain, why the output signal in my verilog testbench isn't changing?

I'm trying to build a module that does tasks on both posedge and negedge.
For testing purposes, I've built a module that receives a clock and returns one signal.
The signal is being set to 1 on posedge, and set to 0 on negedge- I expect it to be a copy of clock signal.
Everything is compiling and synthesizing without errors, the testbench is being run- but the output signal doesn't change, it stays at zero.
I am new to verilog, so maybe I'm missing something obvious.

Here is my module-

module mytest( clk, rst, led );
input clk, rst;
output led;

reg r_out = 1'b0;

always @ (*)
begin

@(posedge clk)
begin
r_out <= 1'b1;
end

@(negedge clk)
begin
r_out <= 1'b0;
end

end

assign led = r_out;

endmodule


And here is the testbench-

timescale 1ns/100ps
module mytest_tb;

parameter SYSCLK_PERIOD = 100;// 10MHZ
reg SYSCLK;
reg NSYSRESET;
wire w_led;

//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;

//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  mytest
//////////////////////////////////////////////////////////////////////
mytest mytest_0 (
// Inputs
.clk(SYSCLK),
.rst(NSYSRESET),

// Outputs
.led(w_led)

// Inouts

);

initial
begin
SYSCLK = 1'b0;
NSYSRESET = 1'b0;
end

endmodule


Thanks in advance!

• For synthesis, you cannot have @(*), @(posedge clk) and @(negedge clk) in the same always block. I'd expect an error for this; if not, there should at least be warnings. There must only be one @ and it needs to next to always. – Greg Jun 13 '17 at 15:01
• @toolic - I chose a bad example. The question is not about copying clk signal, it's about modifying register on both posedge and negedge. Thanks anyway! – Karlis I. Jun 14 '17 at 14:17
• @greg - I was told that my approach is wrong. I'll clarify with some more people and report here. – Karlis I. Jun 14 '17 at 14:19

## 1 Answer

So, I was pointed out that this is a wrong approach.

The problem in question should have been solved by using a Finite State Machine- that would eliminate the need for additional actions on negedge.

As for the question itself- why doesn't the test work- that's because

always @ (*) begin
@ (posedge clk)
...
@ (negedge clk)
...
end


is incorrect syntax. Correct would be

always @ (posedge clk) begin
...
end
always @ (negedge clk) begin
...
end
`