could anyone explain, why the output signal in my verilog testbench isn't changing?
I'm trying to build a module that does tasks on both posedge and negedge.
For testing purposes, I've built a module that receives a clock and returns one signal.
The signal is being set to 1 on posedge, and set to 0 on negedge- I expect it to be a copy of clock signal.
Everything is compiling and synthesizing without errors, the testbench is being run- but the output signal doesn't change, it stays at zero.
I am new to verilog, so maybe I'm missing something obvious.
Here is my module-
module mytest( clk, rst, led ); input clk, rst; output led; reg r_out = 1'b0; always @ (*) begin @(posedge clk) begin r_out <= 1'b1; end @(negedge clk) begin r_out <= 1'b0; end end assign led = r_out; endmodule
And here is the testbench-
`timescale 1ns/100ps module mytest_tb; parameter SYSCLK_PERIOD = 100;// 10MHZ reg SYSCLK; reg NSYSRESET; wire w_led; ////////////////////////////////////////////////////////////////////// // Clock Driver ////////////////////////////////////////////////////////////////////// always @(SYSCLK) #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK; ////////////////////////////////////////////////////////////////////// // Instantiate Unit Under Test: mytest ////////////////////////////////////////////////////////////////////// mytest mytest_0 ( // Inputs .clk(SYSCLK), .rst(NSYSRESET), // Outputs .led(w_led) // Inouts ); initial begin SYSCLK = 1'b0; NSYSRESET = 1'b0; end endmodule
Thanks in advance!