I have a setup as shown in the schematic below. I am using AD9833 DDS to generate a sine wave with ~300mV DC and ~600mVpp signal. I am sending this though a RC high pass and sending this over as first input to an AD620 in-amp. The other input to the in-amp is ground. I am adding a buffered voltage of 1V to set the output common mode as suggested in the data sheet. The first scope capture shows node A (the input sine wave to the inamp). The output is shown in the second capture and as you can see the chip is railing(or is unstable, I dunno). I can't figure out what is going wrong. The gain should be simply ~1.5, so there should be no reason for this weird output. What I have messed up in the design? I have probed all nodes to make sure the voltages are correct. Schematic Node A Output

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    \$\begingroup\$ Are your graphs simulations results or measurements on the real circuit? If simulation results, did you run the sim long enough for transients on C1 to settle out? If physical, could R1 be shorted? \$\endgroup\$ – The Photon Jun 14 '17 at 5:17
  • \$\begingroup\$ These are measurements on a real setup, R1 isn't shorted. In simulation, the output is as expected and as you noted, the output does take some time to settle. \$\endgroup\$ – user1155386 Jun 14 '17 at 5:20
  • \$\begingroup\$ Well, something's broke. The negative half cycle looks okay, but then the positive half cycle looks like you're driving a comparator rather than an in-amp. Retouch all your solder joints. If that doesn't work, replace the chip with a new one. \$\endgroup\$ – The Photon Jun 14 '17 at 5:27
  • \$\begingroup\$ Even the negative cycle looks messed up. It does look comparator-ish. I changed the IC. However, I see the same output. \$\endgroup\$ – user1155386 Jun 14 '17 at 6:13

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