I'm designing a 4 bit ALU as a project. I have circuits that can calculate addition, subtraction and bitwise logic operations - my question is, do I tie A & B (4 bit inputs) to every circuit that performs an operation/function, meaning every function is carried out at once, and use a multiplexer to select which output I want? Or is there a more efficient/elegant way of performing just the operation I want on A & B? I'm not sure (traditionally) how this is done.

  • \$\begingroup\$ Usually you generate a K-map or truth table and derive the equation from there. \$\endgroup\$ Jun 14, 2017 at 16:48
  • \$\begingroup\$ I understand that, I have the functions working, but do I use the multiplexer to select the result? Or to select a singular function (not allowing other functions to calculate)? \$\endgroup\$ Jun 14, 2017 at 16:49
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    \$\begingroup\$ Traditionally in a simple design you let all of them run at once and choose only the result of interest. Only letting one run could perhaps be interesting from a power consumption perspective, but would add some challenges to implement. \$\endgroup\$ Jun 14, 2017 at 17:03
  • \$\begingroup\$ @ChrisStratton Perfect, just the answer I was looking for. Thanks \$\endgroup\$ Jun 14, 2017 at 17:06
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    \$\begingroup\$ @eddiewastaken It's not precisely an either-or situation. Many things are calculated in parallel and selected for. But others cause a change at the beginning and there's no mux at the end to select between outputs. For example, subtraction and addition are usually NOT done in parallel, using a separate adder and separate subtractor, with a mux at the end to pick. Rather, it's usually just an adder (no subtractor) but with one of the inputs inverted and the carry-in set to 1. If you are looking for a perfect bright line answer, there isn't one. \$\endgroup\$
    – jonk
    Jun 14, 2017 at 22:05

2 Answers 2


Look up the detailed design of SN74181 from Texas Instruments. Every logic gate will be shown. Here is a portion, from http://www.ti.com/lit/ds/symlink/sn54s181.pdf

enter image description here

  • \$\begingroup\$ So is every function simultaneously calculated, and the control bits purely just select the result you want? \$\endgroup\$ Jun 14, 2017 at 17:02
  • \$\begingroup\$ Examine the top right cluster of gates, used to generate Carryout. Examine the top left gates, where the 4 S0...S3 bits enter, to select the function. Examine the Carryout pin, and look for any way to inhibit it with various combinations of S0...S3. For fun, examine the AMD2901 4-bit bit-slice. \$\endgroup\$ Jun 15, 2017 at 3:50

Waste of MUX to combine separate logic gates. MUX is the ultimate any gate. 4way pass-through such as 74CBT3253 make chain comparisons without ripple. From magnitude test we can instantly solve all slices of A-B's borrow, B-A's borrow, or A+B's carry.

Series Prefixed Subtractor

With CMOS, no free XOR across coils, so 74LVC2G86 (the smaller chip) handles that. Also dropped Zero as redundant to magnitude. 8 slices of 6nS MUX with XOR


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