I'm trying to understand what happens to binary results after building same VHDL sources using Xilinx latest ISE. I have heard conflicting information about the resulting bit/bin files.

Is the expectation that in two builds bit and bin files result in the exact same binaries reasonable?

Does host OS (Windows vs. Linux) influence the resulting binaries?

Can I do MD5 on two files from different builds and expect them to match?

  • \$\begingroup\$ Xilinx puts a timestamp in their bitfiles, so you will not get an exact match. The timestamp is ASCII formatted and right at the start of the bit file. Other than that, for ISE you should be able to reproduce the exact same results (assuming you build using the same seed for the PRNG) \$\endgroup\$ – ks0ze Jun 19 '17 at 17:38

There is an option to randomize the build process, which IIRC is enabled by default.

As FPGA layout is an optimization problem with high complexity, it is not possible to find the globally optimal layout in a sensible time frame. The compiler instead starts with a random but correct layout, and performs local optimizations on it, until no further optimizations are possible, then checks if the layout satisfies timing requirements.

If the FPGA is close to getting full, this randomization is often the difference between passing and failing timing, so restarting compilation after a failure may give you a working result. Without the randomization, failing timings would reproducibly fail in the next iteration as well.

For production, I'd do ten to twenty different builds, pick three with the best timing margins and actually test them on real hardware at different temperatures (typically, 0° and 55°).

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  • \$\begingroup\$ Can you elaborate please on which settings deals with randomization? If the randomization is disabled, would it be somehow be forced by the build process if design takes almost all FPGA? What about in the case of failing timing constraints; if randomization is disabled, is it forced in the next run? \$\endgroup\$ – Hinko Kocevar Jun 15 '17 at 9:46
  • \$\begingroup\$ @HinkoKocevar, sorry, I normally use Altera FPGAs, so I don't know the Xilinx toolchain. Layout randomization is a standard technique that all vendors implement. I'd probably look for a "seed value" setting in the project options. \$\endgroup\$ – Simon Richter Jun 15 '17 at 9:49
  • \$\begingroup\$ I got stuffed hard by this on one toolchain (Quartus? It was a while ago), the thing seeded the PRNG based on a hash of the file, but it calculated the hash before stripping the comments. Combine with a version control setup that put the last commit message in a special line at the top of the file and you could check in a build that worked reliably on your system, check it back out and have it fail timing when you rebuilt it... Oh how we laughed. If you enable multi threaded place and route on Vivado, you also get a non deterministic build, I don't know about ISE. \$\endgroup\$ – Dan Mills Jun 15 '17 at 11:37
  • \$\begingroup\$ Can you give an estimate of "close to getting full"? e.g. when your resource usage reaches x% then you would start to keep an eye on randomization? \$\endgroup\$ – user3528438 Jun 15 '17 at 13:14
  • \$\begingroup\$ @user3528438, it always affects timing -- some builds will be marginal, others have lots of slack, so it can always pay off to have multiple builds and use the one with the best timings. Where it becomes a major factor is dependent on your design -- if you have a wide fast bus, 40% can be a huge problem already because there are many paths to keep constrained, while a design that is clocked at a few hundred MHz can go up to 90% without trouble. The worst case I've seen was 95% full, 36 bit wide DSP chain at 400 MHz with lots of multipliers. Two weeks to compile, 4% chance of success. \$\endgroup\$ – Simon Richter Jun 15 '17 at 16:43

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