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I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was wondering that is it possible that netlist generated out of same VHDL/Verilog source files for FPGA be used for ASIC design flow as well to carry forward further design developments. I know netlist gets generated after the synthesis stage which depends on synthesis tools of the particular company say Xilinx, ALTERA, Synopsys etc. (some back-end stuff which I'm not much aware of), but a netlist is nothing but a description of the connectivity of modules Right! providing nothing more than instances, nodes, and perhaps some attributes of the components involved. So, going back to the question "Can the same netlist be used for ASIC flow as well as FPGA design flow?"

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  • \$\begingroup\$ Not a complete answer, but google "Altera HardCopy". The Quartus tools can compile a design for FPGA, and then transfer that netlist to a matching ASIC design. \$\endgroup\$ – Tom Carpenter Jun 15 '17 at 19:35
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Assuming the same logic cells or library cells are available on both FPGA and custom ASIC process and the cells with the same functionality have the same name, then yes, you could use the netlist for either.

If only the cellnames are different you could do a search and replace to translate it.

But I do not expect this to be the case as FPGA library cells are usually more complex to offer more flexibility.

Custom ASIC libraries usually only include very basic logic cells in order to keep things small (in size) because as you know, size = money.

You could in theory make a translation library to use FPGA netlist on an ASIC. But creating a new netlist specifically for the ASIC library and the cells which it has available will usually result in a more efficient and smaller design as you get rid of the overhead which will always be there in a netlist for an FPGA.

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A generic RTL netlist might be fine, but not a technology specific netlist. The former is just the same as your HDL code, but re-expressed at a gate level, but typically arranged to fit better for your targeted technology.

Since you still need the ASIC synthesis tools, you might as well start with your HDL in both cases... not to mention, the advantages of allowing the tools to target the technology you want without having to "undo" a previous targeted technology.

Yeh, I don't know, maybe, but, don't do that.

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