# Output voltage ripple

I am trying to understand the boost PFC and how its controller works.

The output voltage always contains a voltage ripple depending on the capacitor value, but shouldn't the voltage loop reduce this ripple overtime and after some time there will be no ripple? I know it's due to the charging and discharging of the capacitor but, from a systems theory point of view, why is there always an error?

• What is "the boost PFC" and its controller? (Link, description, diagram, etc.) Power-factor correction is used on AC systems and ripple on DC. What "voltage loop"? Is this a switch-mode power supply question? Please replace some of your commas with full stops to break your paragraph into sentences. – Transistor Jun 15 '17 at 17:50
• The output has ripple at the switching frequency and its magnitude is also dependant on loading. What do you mean by "voltage loop"? There is only no ripple when the diode that feeds the output capacitor is "perfect" and the load is zero and the capacitor has no leakage. – Andy aka Jun 15 '17 at 18:05

In a PFC (in contrast to a conventional DC-DC converter) there will always be substantial ripple at twice the mains frequency.

The reason for this is that the control loop is attempting to force the input current to follow the input voltage.

Because of this the output voltage loop bandwidth has to be very low, or it would interfere with the input current shaping, causing the input current to be different from the goal. (By forcing the output voltage ripple to minimum).

For a discussion of the challenges you can see this paper:

Steady-state dc voltage ripple discrete analysis of PFC with estimated second-order harmonic compensation for achieving satisfactory performance

Firstly all switched mode converters will have ripple on their output when supplying a load. The controller can control the long term average output voltage but within a cycle the current supplied through the inductor must vary and hence if the load current is constant the voltage on the output capacitor will also vary.

The magnitude of this ripple will depend on a number of factors including switching frequency, load current, capacitance of the output capacitor, inductance of the inductor and parasitic losses in the switching components.

Secondly lets look at the case of active power factor correction. A traditional switched mode mains power supply without active PFC looks like.

Input -> Rectifier -> primary capacitor -> Flyback converter -> output capacitor.

The problem with this design is that it's power factor is shit. Current is only drawn from the input on the peaks of each voltage waveform.

So we change our design to add power factor correction.

Input -> Rectifier -> small primary capacitor -> PFC boost -> Main primary capacitor -> Flyback converter -> output capacitor.

The controller for the PFC boost converter is trying to satisfy two goals.

1. On short time-scales, keep the input current as close as possible to proportional to the input voltage and hence the input power factor as close as possible to 1.
2. On longer time-scales, maintain the desired voltage (usually 380V) on the primary capacitors.

So we have two sources of ripple on the output of the PFC boost.

1. The switching frequency ripple that every switched mode converter has.
2. Ripple at twice the input frequency caused by the varying input power through the cycles of the input waveform.

This ripple doesn't really matter because the output of the PFC boost is not the final output of the power supply and it is most likely smaller than the ripple on the primary capacitors would be if you did not have the PFC stage.

You have quite unusual set of terms connected together. A seasoned electronist would say that it looks out random. Assuming you can understand the control theory the only thing that I can to do to rectify your text, is to give an explanation for PFC in control theory terms:

PFC is needed because without it the electronic power supplies draw non-sinusoidal current altough the mains voltage is sinusoidal. That means a heavy unnecessary load to the mains voltage production and distribution system. The ideal would be that the mains voltage is loaded linearly and resistively.

PFC tries to keep the mains loading current every moment as G x voltage. G is a slowly varying factor when compared to the mains frequency. It can be considered as "effective conductance". In power supplies there's an intermediate energy storage capacitor as a buffer to make it possible.

This could in practice be fully transparent, if the input current shaping and output voltage stabilization were separate processes and had their own energy storing capacitances. If one tries to be ecomomical, he has only single, hefty sized capacitor and a control system that tries to keep in zero some combination of input current nonlinearity and output voltage error. Unfortunately that causes some ripple to the output voltage when the DC output current changes rapidly.

The ripple that John D is referring to isn't the same as the one you're talking about. The one he's talking about arises from the tradeoff between PFC control and output regulation. The one you're talking about arises because of the tradeoff between switching frequency limitations and output voltage ripple. If you go for extremely high frequencies, you could reduce your ripple, at the cost of the components (inductor and MOSFET). That's assuming you're in Discontinuous or Boundary mode. In Continuous mode, you run a greater risk of losing control.