I'm trying to understand precisely input leakage when a GPIO is configured as an input. So I read some MCU datasheets, here is kinetis MK20 datasheets on p15/16 are given input leakage currents.

I've also read this document about input leakage measurements. First cause of input leakage are protection diodes.

Vil/Vih is maximum input voltage to read a low/high level on digital input. We can see, input leakage has maximum values when Vil < Vin < Vdd, in this case when Vdd=3.3V we get ~15µA input current.

  • from theory protection diodes are mostly responsible of leakage current, here is a schottky diode datasheet, in figure 4 is a reverse leakage current vs voltage figure. As you can see current increases with voltage. So, for MK20, when voltage Vil < Vin < Vdd, a current goes from input to GND threw reversed diode, its name is Iind. But, why do we have min leakage current when Vin = Vdd and much higher current when Vil < Vin < Vdd ?

In note (7)

Examples calculated using Vil relation, Vdd, and max Iind : Zind=Vil/Iind. This is the impedance needed to pull a high signal to a level below Vil due to leakage when Vil < Vin < Vdd. These examples assume signal source low = 0V

I'm not sure I've fully understood this note. When we apply Vil < Vin < Vdd, we can read on Input a low level. It means if we have Vil < Vin < Vdd, for example Vin = 3V applied with an output impedance of 100k on digital input, we will have a voltage divider on Input. So on Input we will have 3V x 50/(50 + 100) (voltage divider) = 1V => low logical level will be read.

  • Am I correct?
  • \$\begingroup\$ I'm not really sure what your question is. Can you be concise? Also you talk about a schottky diode then, in the same sentence mention "Vil < Vin < Vdd" - what has this to do with that schottky diode? \$\endgroup\$
    – Andy aka
    Commented Jun 16, 2017 at 9:03
  • \$\begingroup\$ Vil < Vin means that you might no longer read a low level. \$\endgroup\$
    – CL.
    Commented Jun 16, 2017 at 9:14
  • 1
    \$\begingroup\$ This somewhat weird behavior appears to be a result of 5V-tolerant inputs- leakage through an internal Schottky or something similar. \$\endgroup\$ Commented Jun 16, 2017 at 10:10
  • \$\begingroup\$ @Andy aka, I've edited post to reformulate first question. \$\endgroup\$
    – rem
    Commented Jun 16, 2017 at 15:04
  • \$\begingroup\$ @Spehro Pefhany , leakage is because of input protection leakage (also refer datasheet p41), but my question is why at Vdd, leakage decreases so much, when in theory it increases with voltage for a diode. As you said it must be because of Input 5.5V protection, because as we can see leakage current in this zone is 1µA (max 50µA) << leakage in Vil < Vin < Vdd zone. But, I would like to understand precisely how does it work. \$\endgroup\$
    – rem
    Commented Jun 16, 2017 at 15:04

1 Answer 1


I got a precise response from NXP:

screen capture from NXP community web page


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