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I have seen designs for digital clock dividers, which can divide a clock frequency by 1.5, 2.5, etc.

But is it possible to create digital logic which divides a clock by 4/3?

For example, if I have a a 64MHz clock, can I generate a 48MHz clock from it?

For my particular application, I don't need 50% duty cycle.

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  • \$\begingroup\$ yes it is, but i do not know how \$\endgroup\$ – Sclrx Jun 16 '17 at 11:13
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    \$\begingroup\$ You haven't described your circuit - is this with discrete parts or in an FPGA or CPLD? Some applications use a PLL, be nice to know what's available to you. \$\endgroup\$ – TonyM Jun 16 '17 at 11:17
  • \$\begingroup\$ @TonyM - sorry, I should have said. I want to implement this fully inside a Cypress PSoC microcontroller. So I have access to Verilog and hates etc. \$\endgroup\$ – Rocketmagnet Jun 16 '17 at 12:42
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    \$\begingroup\$ Is it possible to divide a clock by 1.5 or 2.5 without using a PLL? The result should be clock with only a small phase jitter. Blocking every third period of a 30 MHz clock to get 20 MHz would result in a heavy phase jitter. \$\endgroup\$ – Uwe Jun 16 '17 at 15:08
  • \$\begingroup\$ with a pll sure, and as already mentioned can do one with jitter without a pll..If you are trying for 48Mhz for USB you want something with a pll. (where is your 65mhz clock coming from, a crystal?) \$\endgroup\$ – old_timer Jun 16 '17 at 20:02
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Digital counters can divide a clock frequency by any integer. Digital logic can't directly multiply frequencies by integer values.

However, you can use a digital counter in the feedback loop around a PLL (phase locked loop). The overall effect is to multiply the clock frequency by the divide value of the counter.

Such PLLs are common in higher end microcontrollers. Take a look at the clock chain of any dsPIC33EP series, for example. There are various dividers and a PLL block that multiplies the clock frequency. Between the PLL and dividers, you can hit quite a range of clock frequencies from a single crystal.

In your case, you only need to divide by 4 and multiply by 3. This can be accomplished by a divider and a PLL. Generally you want dividers to divide by a even number so make the result more square. You may actually want to multiply by 6 (which requires a divide by 6 internally), then divide by 8. Dividing by a power of 2 is particularly easy.

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You can take your 64 MHz and filter (with an LC bandpass filter) to recover the third harmonic (192 MHz). You should also be able to use a ceramic filter with some Q reduction techniques. It's called a frequency tripler.

enter image description here

The 3rd harmonic will be about 42% of the amplitude of the original square wave. Then you use an amplifier to restore the 3rd harmonic amplidue towards decent logic levels and then use a divide by 4.

Or, divide by 4 to get 16 MHz then use a frequency tripler to get 48 MHz. This is probably the safer approach because the componentry is easier to build.

You can always use a PLL like this: -

enter image description here

Fin will be 64 MHz and Fout will be 192 MHz if N=3. All you then need to do is add a divide-by-4 to get 48 MHz or, you start by dividing the 64MHz by 4 to get 16 and feed that into Fin with N = 3 and the output is 48 MHz.

The problem sometimes with PLLs is jitter and the loop filter needs to be designed carefully and you need a VCO (voltage controlled oscillator) that doesn't jitter too much.

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  • \$\begingroup\$ Its very tricky.. \$\endgroup\$ – M.Ferru Jun 16 '17 at 11:35
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    \$\begingroup\$ @M.Ferru some precision has to be employed because there will be some fundamental nuances in the filtered signal but, it is a common enough technique used by RF guys. \$\endgroup\$ – Andy aka Jun 16 '17 at 11:37
  • \$\begingroup\$ It's a way of thinking I have acquire yet ! Do you think it's possible to make a circuit that take in input an unknown frequency periodic signal and then divide it by 4/3? Since the inut is unknown, it's hard to design a good bandpass filter \$\endgroup\$ – M.Ferru Jun 16 '17 at 11:41
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    \$\begingroup\$ @M.Ferru True, that will only work for a certain frequency and some bandwidth around it. But usually that's all what RF designers need. \$\endgroup\$ – Bimpelrekkie Jun 16 '17 at 11:45
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    \$\begingroup\$ @M.Ferru well, the only partially general solution is to use a PLL such as the ADF4111 (example) but, you still have a VCO with a limited lock/pull range. \$\endgroup\$ – Andy aka Jun 16 '17 at 11:54
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In complement to other answers, here are some techniques that haven't been mentioned yet. We're trying to achieve a division by 4/3 = 1.33333, which is also a multiplication by 3/4 = 0.75.

  • Fractional Divider

This circuit flips between two integer division ratios. This is usually implemented inside an IC. You get a counter and a digital comparator like in any divider, but the comparator automatically switches between two values.

For every 4 input cycles, you want 3 output cycles. Thus you set the division ratio to 1 for 2 counter cycles (which outputs 2 cycles) and you set the division ratio to 2 for 1 counter cycle, which consumes 2 input cycles and outputs one cycle.

Drawback: the output clock does not have a constant cycle time, so the usability of this circuit depends very much on the application.

Let T = 1/64MHz = 15.6 ns

This circuit will output two 15.6ns cycles followed by one 31.2ns cycle. If the circuitry downstream works at 48MHz but can't be overclocked to 64MHz, then it will choke on the 15.6ns cycles.

This type of divider is more usually used for higher ratios like divide by 31.5 or the like, in which case if some cycles are 31 or 32 original clock, the length isn't that different, so you don't get timing problems. But you cant feed that clock to an ADC/DAC... or any kind of stuff where phase noise/jitter matters...

  • PLL

Multiply by 3 using a PLL, then divide by 4 using the output divider.

This will give you a nice, 50% duty cycle clock. This can clean jitter, or add more jitter depending on noise, bandwidth, and other PLL/VCO specs.

  • Other solutions mentioned above

Think about what the circuit using this clock requires.

Output waveform timing?... (Needs 50% duty cycle? Needs cycles to be all the same duration or can tolerate different cycle times?...)

Need to change frequency/division ratio on the fly or not?

Phase noise requirements?

For example,

  • Andy's third harmonic filter is tuned to only one frequency by component values, so it is not flexible. But it will give a clean waveform, with a bit of subharmonics depending on filter selectivity.

  • Bimpelrekkie's frequency doubler depends on gate propagation times, so output waveform duty cycle and uniformity of cycle length will be poor. If the gates used are too fast, output cycle time may be too short for downstream circuits. But it's simple, cheap, and will work over a wide range of input frequencies.

  • The fractional divider is less problematic, but still, some output cycles will be longer than others.

  • The PLL is the swiss-army knife, plus you can usually reprogram it on the fly, but of course... you have to have a PLL! Adds cost and complexity, unless your micro happens to have one lying around.

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Many clock signals have an approximately 50% duty cycle, but many devices are only interested in rising edges or only interested in falling edges. A circuit to divide a signal by 2.5x will generally respond to all clock edges, but then produce an output which is e.g. high for 2 clock edges and low for three of them. If the input wave is symmetrical, the output wave will be periodic but non-symmetrical. If the input wave is not symmetrical, the output wave will be "wonky". For example, a symmetrical reference wave fed into the aforementioned divide-by-2.5 circuit would yield:

-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ -- original
LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL -- edges
--___--___--___--___--___--___--___--___--___--___--___--___ -- output

Dividing that 2.5x clock again by 2.5x would yield:

--___--___--___--___--___--___--___--___--___--___--___  -- original
L_L__L_L__L_L__L_L__L_L__L_L__L_L__L_L__L_L__L_L__L_L__  -- edges
-----_______-----________-----_______-----________-----  -- output

Every high pulse is consistently five half-pulses of the original wave, but the low pulses alternate between being seven and eight half-pulses of the original wave. As a result, the time between consecutive rising edges (and likewise the time between consecutive falling edges) alternates between 12 and 13 half-pulses.

Dividing a symmetrical signal by a half-multiple in cases where the output does not have to be symmetrical is the one situation where fractional division can yield a clean output without having to use a PLL or other means of generating a signal which is faster than the original.

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  • \$\begingroup\$ Thanks supercat, but do you think it's possible to divide by 4/3 ? \$\endgroup\$ – Rocketmagnet Jun 17 '17 at 9:23
  • \$\begingroup\$ Creating a uniform signal whose frequency is 4/3 of the original would require precisely placing clock edges in the new signal that aren't present in the old ones. If one is willing to have a signal where some cycles are half again as long others, and one doesn't care about pulse widths, it would be possible to do that without having to precisely place any edges, but if that is not acceptable the approaches discussed in other answers will be needed. \$\endgroup\$ – supercat Jun 17 '17 at 18:11
  • \$\begingroup\$ I understand that. As I said in my question, I don't need a 50% duty cycle. And I also don't mind that the rising edges aren't all going to be equally spaced. With that in mind, do you think it's possible to do this using digital logic? \$\endgroup\$ – Rocketmagnet Jun 17 '17 at 20:27

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