In complement to other answers, here are some techniques that haven't been mentioned yet. We're trying to achieve a division by 4/3 = 1.33333, which is also a multiplication by 3/4 = 0.75.
This circuit flips between two integer division ratios. This is usually implemented inside an IC. You get a counter and a digital comparator like in any divider, but the comparator automatically switches between two values.
For every 4 input cycles, you want 3 output cycles. Thus you set the division ratio to 1 for 2 counter cycles (which outputs 2 cycles) and you set the division ratio to 2 for 1 counter cycle, which consumes 2 input cycles and outputs one cycle.
Drawback: the output clock does not have a constant cycle time, so the usability of this circuit depends very much on the application.
Let T = 1/64MHz = 15.6 ns
This circuit will output two 15.6ns cycles followed by one 31.2ns cycle. If the circuitry downstream works at 48MHz but can't be overclocked to 64MHz, then it will choke on the 15.6ns cycles.
This type of divider is more usually used for higher ratios like divide by 31.5 or the like, in which case if some cycles are 31 or 32 original clock, the length isn't that different, so you don't get timing problems. But you cant feed that clock to an ADC/DAC... or any kind of stuff where phase noise/jitter matters...
Multiply by 3 using a PLL, then divide by 4 using the output divider.
This will give you a nice, 50% duty cycle clock. This can clean jitter, or add more jitter depending on noise, bandwidth, and other PLL/VCO specs.
- Other solutions mentioned above
Think about what the circuit using this clock requires.
Output waveform timing?... (Needs 50% duty cycle? Needs cycles to be all the same duration or can tolerate different cycle times?...)
Need to change frequency/division ratio on the fly or not?
Phase noise requirements?
Andy's third harmonic filter is tuned to only one frequency by component values, so it is not flexible. But it will give a clean waveform, with a bit of subharmonics depending on filter selectivity.
Bimpelrekkie's frequency doubler depends on gate propagation times, so output waveform duty cycle and uniformity of cycle length will be poor. If the gates used are too fast, output cycle time may be too short for downstream circuits. But it's simple, cheap, and will work over a wide range of input frequencies.
The fractional divider is less problematic, but still, some output cycles will be longer than others.
The PLL is the swiss-army knife, plus you can usually reprogram it on the fly, but of course... you have to have a PLL! Adds cost and complexity, unless your micro happens to have one lying around.