# Circuit diagram of synchronous sequential circuit using rising edge triggered D-type flip-flops

How do I draw a circuit diagram for this system using the "one flip-flop per state" technique? UPDATE:

This is what I have so far, but I'm getting so confused. The first step toward implementing a state machine is to draw the state diagram that it will implement. A state diagram shows every state that the machine can be in, along with all of the conditions that cause it to switch from one state to another (or not).

A timing diagram is actually an incomplete specification for a state machine, because it does not cover all of the possible combinations of current state and inputs. This means that you can come up with one possible answer, but there may be others. In this case, you should pick the simplest answer that meets the requirements.

The outputs are simple; we can see that OUT1 corresponds to state B and OUT2 corresponds to state D.

In the given timing diagram we see the following transitions:

• A → A when IN1 = 0 and IN2 = X
• A → B when IN1 = 1 and IN2 = 0
• B → C when IN1 = 0 and IN2 = 0
• C → A when IN1 = 0 and IN2 = 0
• B → D when IN1 = 1 and IN2 = 0
• D → D when IN1 = 0 and IN2 = 0
• D → A when IN1 = 0 and IN2 = 1

The following combinations are unspecified:

• state A when IN1 = 1 and IN2 = 1
• state B when IN1 = 0 and IN2 = 1
• state B when IN1 = 1 and IN2 = 1
• state C when IN1 = 1 and IN2 = 0
• state C when IN1 = 0 and IN2 = 1
• state C when IN1 = 1 and IN2 = 1
• state D when IN1 = 1 and IN2 = 0
• state D when IN1 = 1 and IN2 = 1

One interpretation is to assume that the unspecified combinations do not cause state transitions.

Other interpretations are possible — for example,

• We could assume that IN2 is a "reset" input, because in all cases when it is asserted, the next state is A.
• We might also assume that state C always makes the transition to state A, because we never see it do anything else.
• That just leaves the case for state D when IN1 = 1 and IN2 = 0 — I would be inclined to leave it in state D. It's my impression that state D (and OUT2) is intended to "latch" pulses on IN1 that are two or more clocks wide.

Together, these assumptions cover all of the unspecified transitions.

Only after you have a complete state diagram can you start designing the logic for an implementation. The nice thing about "one-hot" designs (one FF per state) is that the logic pretty much follows the state diagram one-for-one.

Sorry, no full solutions to homeworks, only quidance!

Take 4 ff:s of D-type. Lets's name them a,b,c and d according the states. Everyone gets the same clock. Everyone have a different gate that produces the D-input for the ff. The gate at the D-input of ff X should give out 1 exactly when the variables have such combination that the next state should be X.

One of the states should be the reset state. The master reset signal sets that ff and resets others.

ADDENDUM: This is more difficult case than I believed (not the circuit, it's simple). But let's add some clarifications.

The pulse diagram has named states a, b, c and d for the machine. It's especially simple because the original demand was the states are directly shown by the outputs of the flip-flops (=one ff per state). That's why I named the flip-flops as the states. In state a only the output of ff a is 1, in state b only the output of ff b is 1, etc...

D type flip-flop copies the logic value from its D-input to its output Q every time when the clock pulse jumps from 0 to 1. To make the Q-output of ff a to 1 at the right moment one must feed 1 to its D-input just when the machine is expected to jump into state a from another state or from state a.

The pulse diagram gives several different cases when the next state is a. Thus quite a complex gate circuit is needed to produce proper input to the D-input of ff a.

The conditions that lead to state b are simpler. The machine jumps to state b (= sets the output of ff b to 1) exactly when the current state is a and the input IN1 is 1. Thus connect to the D-input of ff b the output of an AND-gate. The inputs of that AND are the Q-output of ff a and the signal IN1. There really is nothing more needed to D of ff b. Actually the pulse diagram is shortened. It makes me free to assume that IN2 doesn't affect to the transition from a to b.

The pulse diagram shows 4 different cases when the D of ff a should be =1. they are:

• state is a and IN1=IN2=0
• state is c (I assume a follows c automatically because no alternatives are shown after c)
• state is d and IN2=1
• state is a, IN1=0 and IN2=1

You need a gate circuit (=logic combination circuit) that produces 1 to D of ff a just in these cases. I see it needs a multi input OR and a couple of ANDs and inverters.

Now: try to continue

Hopefully you can see how to produce OUT1 and OUT2.

• "Everyone have a different gate that produces the D-input for the ff." - could please explain what you mean here – DNN Jun 16 '17 at 16:41