I need to calculate the exact sampling time or sampling rate for my setup on a STM32F205. I have the ADC setup as follow:

ADC_DeInit();



I have this form the STM32F20x reference manual

Channel-wise programmable sampling time The ADC samples the input voltage for a number of ADCCLK cycles that can be >modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time. The total conversion time is calculated as follows: Tconv = Sampling time + 12 cycles Example: With ADCCLK = 38 MHz and sampling time = 3 cycles: Tconv = 3 + 12 = 15 cycles = 0.5 μs with APB2 at 60 MHz

But I don't really understand how to use it on my setup.

Any help is welcome and I will provide any extra info if needed.

That depends on the source of the measured signal. Some time is required to charge the ADC input capacitance, so if your signal circuit can't sink / source enough current the sampling time will need to be longer. The longer the sampling time, the slower the ADC sample rate will be. On some STM micros you can use built-in opamps as the input buffers. You can also have the external ones to make readings quicker and more precise.

When you calculate the conversion time you need to:

• From RM (Reference Manual RM0033 for STM32F205) you know that total conversion time is equal to 12ADC clocks + your sampling time. For example if the ADC clock is 12MHz and the sampling time is 84 clock cycles then total conversion time will be 84 + 12 ADC cycles = 8us, and max ADC sample speed = 1/8us = 125kSPS.
• For the max ADC speed in my setup that calculation would be: ADC clock 60MHz RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); / 4 ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;. And then Tconv = 3 ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_3Cycles); + 12 = 15 Max ADC speed = 15MHz / 15 = 1MSPS ??
– Bjqn
Jun 19, 2017 at 9:30
• To be honest, I do not use HAL libraries and only program bare register. But cuople of notes. 60MHz it is THE APB2 clock. ADC clock is after the ADC prescaler and this speed can be max 30MHz. Your calculation is correct. That is the maximum speed archivable when you use DMA. Otherwise Jun 19, 2017 at 9:44
• Nice.. But do i need to add ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; to the Tconv ? Then Max ADC speed = 15MHz / (3 + 5 + 12) = 750kSPS
– Bjqn
Jun 20, 2017 at 9:36
• As I stated I do not know HAL. ADC is much easier to program and understand if just the bare registers are used. You need only to think what the hardware does, not the library + hardware. Jun 20, 2017 at 10:05

I'll let you work out the details for your particular case, but I'd like to add some more clarity.

First off, I've opened up an errata report on RM0410 (the reference manual for my chip) here.

I'll be referencing Reference Manual RM0410 Rev 4, which is the Reference Manual I need for my case. This isn't for your chip. You'll need to find the one for your chip.

ST's chips allow you to choose an ADC sampling time AND resolution.

RM0410 p473. Here are some sampling time options for me. They range from 3 to 480 ADCCLK cycles. I've highlighted them below: They are:

  3 cycles
15 cycles
28 cycles
56 cycles
84 cycles
112 cycles
144 cycles
480 cycles


You can see these from the drop-down menu in STM32CubeMX: Each clock cycle is equal to one ADC clock cycle, called ADCCLK in the RM. The equation for ADCCLK frequency is:

ADCCLK = PCLK2 / prescaler


Where prescaler can be 2, 4, 6, or 8.

Use STM32CubeMX to see these prescaler values from the dropdown menu as well. You'll notice that PCLK2 divided by 2 is greyed out for me, meaning it is an invalid value for my configuration, probably because that would result in an ADC clock that is too fast. Conversion time is based on the bit-resolution you've set for your ADC. Options are 12 bits, 10 bits, 8 bits, or 6 bits.

Conversion time based on ADC resolution is as follows:

12 bits --> 12 ADCCLK cycles
10 bits --> 10 ADCCLK cycles
8 bits -->  8 ADCCLK cycles
6 bits -->  6 ADCCLK cycles


The RM is a bit misleading (hence my errata report above) but here's what RM shows on p452. Take a look at my notes for clarity and corrections: Putting it all together, the equation is:

total_ADC_sampling_time = user_chosen_sampling_time + conversion_time_based_on_resolution


where

conversion_time_based_on_resolution = 1 ADC_clock_cycle/bit_of_resolution x bits_of_resolution


And again, as shown above,

ADCCLK = PCLK2 / prescaler


# Examples:

## Example 1: Let's say I'm doing 12-bit resolution and 480 clock cycles sampling time

My total sampling time is:

total_sampling_time = 480 + 12-bits x 1/bit = 480 + 12 = 492 ADCCLK cycles.


Assuming PCLK2 is 108 MHz (see "Clock Configuration" tab in STM32CubeMX), and prescaler is 8, we know:

ADCCLK = 108/8 = 21 MHz.
1/21 Mhz = ~47.619ns/clock cycle


Total sampling time is therefore:

492 ADCCLK cycles x 47.619ns/clock cycle = 23.429us


Sample rate is

sample_rate = 1/23.429us = 42.682 kHz.


## Example 2: What's my absolute maximum sample rate possible at 10-bit resolution?

For my case, STM32CubeMX greys out the PCLK2 divided by 2 option, so the fastest I can choose is a prescaler of 4. The fastest user-selectable sampling time possible is 3 cycles, and 10-bit resolution adds 10 more cycles, for a

total sample time = 10 + 3 = 13 cycles.

ADCCLK = 108/4 = 42 MHz.
1/42 Mhz = ~23.8095ns/clock cycle


Total sampling time is therefore:

13 ADCCLK cycles x 23.8095ns/clock cycle = 309.5235 ns


Sample rate is

sample_rate = 1/309.5235 ns = 3.230772 MHz!  <=== very fast for a mcu!


# Which ADC sampling time should I choose?

I mean, why all the options?

Here are the available sampling times to choose from:

  3 cycles
15 cycles
28 cycles
56 cycles
84 cycles
112 cycles
144 cycles
480 cycles


Answer: there isn’t really any info on this in the ST Reference Manual that I can find, but essentially, sampling an analog signal more slowly reduces surge "parasitic" drain on the analog line as a result of the sampling process itself, which both draws a tiny current from the analog line and takes time. If your analog line has an extremely small current source capability (think: the analog source "recharging" the capacitance of the analog line can only produce a tiny tiny current to recharge that analog line), then it cannot handle a high sample rate sampling on it. This is, again, because the sampling process itself will draw current, making the analog signal sag (distorting it from its true value), and introducing noise to the analog signal. In such cases you are wise to choose a slow sample rate by setting your sample time to a very long value, such as 480 ADC clock cycles, for example, which is the longest you can choose.

## Rule of thumb:

In short, just choose the longest sampling time you can, to be safe, that will meet your sample rate requirements. If you must sample as fast as possible, do so, increasing sample time (and therefore decreasing sample rate), as required, until your analog signal remains stable and stops fluctuating due to noise you are adding to the analog line as a result of your sampling.

Make sense? Go slow unless you need to go fast. If you need to go fast, ensure you're not going too fast. If you're going too fast, slow down until you're no longer going too fast.

Done.

Quick and dirty way to verify the sampling time; pull a MCU GPIO high right before a sequence of samples start and pull it low right after blocking for conversion to finish. Check the GPIO pin pulse time with oscilloscope and divide by the number of samples taken. This is limited to manually triggered conversions, of course.