I have recently designed a four-layer PCB in KiCad. It is a spectrometer having PIC24EP and a CCD linear image sensor (TCD1304). The layer stack up is as follows:

  1. Signal (no copper pour)
  2. Ground
  3. 3.3 V power plane
  4. Signal (copper pour connected to ground)

The TOP layer is of RED color and the bottom layer is of GREEN color. The middle layers are completely copper pour (no trace in them). Below is the picture of my layout:

Enter image description here

I have read over here about three types of coupling, and I have been trying to reduce as much noise as possible (not even µV, if it is possible to achieve). I have mentioned below how I think my board should be avoiding each type of coupling. However, I am not sure if I understood the concept correctly and maybe I have missed a few things which I don't know yet. That's why I have posted this question. Please review my board and my explanation and help me.

Common Impedance Coupling:

The ground plane behind the TOP signal layer helps in reducing the impedance of the ground (as it has widest area). I have used two pins for GROUND in header J1 to reduce the common impedance coupling.

Electrical Field Coupling:

I have taken care of distance between critical tracks. The analog pin of TCD1304 is far away from the clocks of TCD1304 and oscillator.

Magnetic Field Coupling:

I know that magnetic field coupling can be reduced if there is a large distance between loops and they are aligned at 90 degree to each other. There is a wide distance between TCD1304 clock lines and the ADC pin. However, I can't run horizontal/vertical tracks on top/bottom layers as I think it is not possible (please suggest to each that if I am wrong).

Regarding Return current path:

The return current path of the top layer will be ground plane (as it is just below it) and of the bottom layer will be 3.3 V plane. I think the return current path for oscillator and crystal will be ground plane and as you can see it in layout, it is not interrupted. The return current path of TCD clock lines and analog output line will be just below the signal and hence, it is not interrupted as well.

I am not quite sure about voltage references (LM4041). I want to have very low coupling to them for stable references. I think there is no such problem with my references in my board, but I can consider to place them at the bottom layer if it helps to achieve good performance.

I am not sure about position (at what layer) of the decoupling capacitors. Please tell me best placement for them.

The clock frequency of TCD is 2 MHz. The PIC24EP has 12 MHz SMD crystal. The Fosc of the PIC is 64 MHz. I know maybe most of the things won't matter at this frequency, but I am an undergraduate trying to learn and build things. Please point me towards the right direction.


I have modified my layout as suggested by others (just solved the pads issue). I am working on reducing noise by understanding what others has suggested.

enter image description here

  • \$\begingroup\$ Taking a brief look, I believe your bypass cap layout could be improved. You shouldn't use a via to ground and a separate via on the IC, instead a via to the cap, and a direct trace from cap to IC. \$\endgroup\$
    – Wesley Lee
    Jun 17, 2017 at 1:42
  • \$\begingroup\$ What range of signal frequencies and edge rates are you facing in this design if you are so concern with all this nit picking? This is a 2-MHz device for God's sake... \$\endgroup\$ Jun 17, 2017 at 2:49
  • \$\begingroup\$ @AliChen I just want to learn as much as possible and use the best techniques even if they are not going to improve performance alot. \$\endgroup\$
    – buddha
    Jun 17, 2017 at 3:30
  • \$\begingroup\$ At those frequencies, you shouldn't think much about these effects \$\endgroup\$
    – abhiarora
    Jun 18, 2017 at 14:35

4 Answers 4


Looks like AnalogSignal is adjacent to MasterClear, which comes from external signal (J3). MC is bypassed, but cap ESL & ESR prevent high-frequency bypassing; also, the bypass Cap converts trash voltages into trash magnetic fields.. Add 1Kohm in lower right on PCB, near connector J3, to form LowPass, and also limit the currents that would become magnetic fields. [in PCB layout, insert a new resistor where the "J3" text shows, just to left of pin#1 of J3. Again, this assumes MC comes from off the PCB, and brings in trash.]

[The cap on MC is a centimeter away from AnalogSignal, and orthogonal. The problem is the adjacent pins used by AnalogSignal and MC, causing Efield and Hfield coupling.]

Your 3 lower left signals (digital, pins 3/4/5) into the sensor will also convey MCU trash into the sensor, because the MCU is never quiet and the logic-levels of your 3 signals will never be clean. I suggest installing 3 resistors, to left of Y1 crystal, in series, and then 3 capacitors SMT to GND; this is another LowPass Filter, used to shunt the MCU trash to GND; goal is keep the trash currents out of the sensor; to do this, use high value resistors (which inherently limit the trash currents into sensor) and/or 100PF capacitors near sensor pins 3/4/5 to shunt most of the trash OUTSIDE the sensor; the sensor ESD and MOSgates (3-5pf) will still admit some of the MCU trash. Better yet is a buffer IC, with private VDD, between MCU and Sensor.

Regarding Efields coupling onto Analog Sensor #21, bring metal from pin#20 and pin#22 (gnds) close around the Analog signal; these gnds will capture yet more of the Efields. If you can make the Analog trace even thinner (10 mils or 8 mils) and bring the other analog gnds close, even more Efields get intercepted by GNDs. And if you wish, add 100pF SMT onto the Analog pin, causing a very beneficial voltage-divider action between Efields coupling through the air (very small capacitance) and the inherent C_out of the sensor + C_in of MCU + 100pF; your sensor might not tolerate any additional such capacitance.

Regarding magnetic coupling, the underlying planes (GND and VDD) tend to intercept Hfields; I cannot put better attenuation numbers on these topologies just yet, but we are working on that. We've discussed reducing the HF from Master Clear, using a resistor near J3 (assuming J3 brings in a external MC). I note a bypass cap C10 just one pin away from Sensor Analog input to MCU; can you place that bypass cap UNDER the MCU, on opposite side of PCB? How serious is this?

Using $$Vinduce = MU0 * MUr * Area/(2*pi*Distance) * dI/dT$$, this becomes $$2e-7 *Area/Distance * dI/dT$$

Assuming area is 2mm * 2mm, distance is 2mm, and dI/dT is 10mA/1nS, the Vinduce is 2e-7 * 2mm * 10^7 amp/sec = 4 milliVolts. Thus keeping the bypass cap magnetic fields away from the Analog input traces is necessary for ENOB of 10 bits or better.

EDIT Years ago I designed a 4-channel 6MegaSample/sec 12 bit Av=2/4/8/16 camera-pixel digitizer. The data exited through 4 FiberOptic transmitters. Other than SPI bit streams to set gains and offsets (via 16-bit DACs) and image-sizes and frame rates (up to 100,000 frames/second if image was only 8X8), the only incoming "trash" were the DC power lines and the system clock. Cascades of PI filters rejected most of the (remote) SwitchReg trash. One careful PCB design aspect was ----- placing the OpAmp bypass caps ---> orthogonal <--- to the signal path. I had 12 bits/+-2.5 volts, following Av= 16x, thus quantization floor was 16uV*5 = 80 microVolts. What would have been the injected HF self-induced feedback? Assume 1mm cube (area/distance) and 1mA/10nS dI/dT.

Vinduce = 2e-7 * 1mm * 10^5 Amp/second = 2e-10 * 1e+5 = 2e-5 = 20 microVolts.

Given I have no control over the R+C filter just prior to the ADC, I had no control over the "dI/dT". Result? Absolutely no visible artifacts in the recovered images. Overdesign? possibly so. But customer was very pleased.

[Regarding the placement of bypass capacitors ORTHOGONAL to AnalogSignal --- yes, we want to minimize the Mutual Inductance.]

[In the original PCB plot, notice the large amount of "black" around Sensor pin21 "AnalogSignal". Fill in that black, as close as you can, with copper that is grounded.]


simulate this circuit – Schematic created using CircuitLab

What really happens when GROUNDED FOIL is placed on same layer as an Analog Signal, and very close? Incoming Efield flux is mostly gathered by the GROUNDED FOIL, reducing the "displacement current" induced in the Analog Signal.

  • 1
    \$\begingroup\$ Detailed answer to my question. But i have few more questions. Q1) You said "the bypass Cap converts trash voltages into trash magnetic fields". I am assuming trash voltages (high frequency) generates high frequency current and therefore, it induce magnetic field. However, if my caps of small size? Then their current loop area will be less and hence less will be the magnetic fields??? \$\endgroup\$
    – buddha
    Jun 19, 2017 at 16:04
  • \$\begingroup\$ Q2) You said "Add 1Kohm in lower right on PCB, near connector J3, to form LowPass". Where to place resistor? I didn't get you there \$\endgroup\$
    – buddha
    Jun 19, 2017 at 16:05
  • \$\begingroup\$ Q3) You said " One careful PCB design aspect was ----- placing the OpAmp bypass caps ---> orthogonal <--- to the signal path.". Is it due to fact their current loop will be perpendicular to each other and hence, their mutual inductance will be less? \$\endgroup\$
    – buddha
    Jun 19, 2017 at 16:11
  • \$\begingroup\$ Q4) You said "Regarding Efields coupling onto Analog Sensor #21, bring metal from pin#20 and pin#22 (gnds) close around the Analog signal; these gnds will capture yet more of the Efields.". I didn't get it completely? \$\endgroup\$
    – buddha
    Jun 19, 2017 at 16:13
  • \$\begingroup\$ Yes. I do have similar questions @analogsystemsrf \$\endgroup\$
    – abhiarora
    Jun 19, 2017 at 16:14

Being as you have put your design up for review let me high light two areas where there is no reason to have such sloppy connections to your microcontroller pads. You should make traces come off the pads at same width of the pads and then possibly widen if you should so desire.

Example 1:

enter image description here

Example 2:

enter image description here

You are asking other esoteric questions and not even paying attention to trivial details.

  • \$\begingroup\$ I will update my layout. Thanks for the suggestion. By the way, please do mention reason behind to have same width at pads? \$\endgroup\$
    – buddha
    Jun 17, 2017 at 3:29
  • \$\begingroup\$ Is it related to signal reflection due to impedance mismatch? \$\endgroup\$
    – buddha
    Jun 17, 2017 at 3:37
  • 4
    \$\begingroup\$ No. It relates to two main factors. A) Elegance of your layout where it shows you took the care in your design. B) Pad layouts are typically designed with special care of pad width to pad spacing so that hopefully you can get solder mask to have a consistent profile between pads. This helps greatly in being able to devise the solder paste profile that is consistent for all pads on a package so as to allow even soldering for every lead while at the same time preventing solder bridges between pads. With the extra copper as in the above examples the solder mask will have a (continued) \$\endgroup\$ Jun 17, 2017 at 5:07
  • 1
    \$\begingroup\$ (continued from above) different profile at those pads. The narrower space between the copper and adjacent pad could also get too close to the minimum design rules for your copper width and spacing and lead to potential problems of etching reliably when the raw PC board fab is created. \$\endgroup\$ Jun 17, 2017 at 5:10

If your microprocessor has a feature to stop the cpu during acquisition, use it.

Now, your analog reference layout has problems.

The PIC's analog reference is the voltage between AREF and AGND. However the reference decoupling cap is not connected between AREF and AGND, it is on the bottom layer instead, and it has no vias, which means its ground pin will be connected to whatever part of the bottom copper pour happens to be there... you don't know what currents flow in this copper pour, as you put all other decoupling caps there and it has very few vias to the main ground plane.


  • Remove pour on bottom layer.
  • Extend power plane only under microcontroller
  • Don't feed sensor from noisy microcontroller's power, use a small LC filter
  • Put ground vias on your decoupling cap!
  • Put everything on toplayer, assembly will be cheaper...

THings you need to study and learn before you can design good boards.

1) DRC rules for layout and standard practice ( at least 30 pages) Findable on web

2) EMI Design book from Henry Ott or similar which includes radiated and conducted noise: egress & ingress reduction , 20 common solutions such as CM ferrite beads, differential controlled impedance, gaurd tracks, copper pour etc. (There may be more up to date books, but less thorough)

3) Source a good quality board shop with automated DRC and low cost

e.g. Sierra Proto Express in "Silicon Valley" , CA

2, 4, 6 layer low-cost, quickturn prototype PCB fabrication
Pre-defined specifications
Automatic file verification
Free instant DFM on your file
Find whether your design matches No Touch specs
See layer images as seen by our system to ensure proper registration, polarity etc
Get a Netlist compare report
No holds processing
Minimum finished hole size down to 8 mils
Trace /space down to 4 mils
Now allows 0.250" (250 mils) Non-Plated Holes
RoHS-Compliant (Lead-free material and surface finish)
Instant online quoting, ordering and tracking

"standard specs" https://www.protoexpress.com/content/stcapability.jsp "Better DFM" https://www.protoexpress.com/betterdfm/

e.g. Signal Checks

Conductor Width
Annular Ring
Drill to Copper
Hole Registration
Text Features
Missing Copper
Features Connection
Missing Holes
Unconnected Lines
Rout to Copper

Plane Checks

Drill to Copper
Annular Ring
Conductor Width
Thermal Air gap / Spoke Width
Missing Copper
Rout to Copper
Drill Registration
Clearance smaller than hole

Solder Mask Checks

Solder Mask Clearance
Coverage  Rout to Mask Spacing
Missing Solder Mask Clearance
Exposed Lines
Partial Clearances

Silk Screen Checks

Silk Screen to Mask Spacing
Silk Screen to Copper Spacing
Silk Screen to Hole Spacing
Silk Screen to Rout Spacing
Line Width
Text Height
Silk Screen Over Copper Text

Drill Checks

Hole Size
Duplicate Holes
Hole Spacing
Touching Holes
Plane Shorts
Holes to Rout
Missing Holes

4) DFM design for manufacturability

5) DFT design for testability

6) DFC design for cost

The above all just part of a series of design optimizations. All together, were called DFX coined by Nortel

  • \$\begingroup\$ Please do mention what needs to be done and why? I am assuming you are suggesting me to keep the width of tracks coming out of pads same as of pads. Is it related to signal reflection due to impedance mismatch? \$\endgroup\$
    – buddha
    Jun 17, 2017 at 3:36
  • \$\begingroup\$ @buddha: Yes, same or lower track width. Also, your your tracks shouldn't be bending so close to the other pads (see pin1 & 2 and pin 4 & 5). Or better yet, set your design rule parameters beforehand. I'd suggest you keep a copy of this file and create a new PCB file. Then you'll be able to see the difference and maybe understand better. \$\endgroup\$
    – Sachin
    Jun 17, 2017 at 6:07
  • 1
    \$\begingroup\$ tracks are designed less than pad size for solder surface tension reasons when liquidus stage during reflow to help self centre \$\endgroup\$ Jun 17, 2017 at 15:00

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