I saw this VGA demo for a 640x480 monitor


and I would like to run it on my monitor using a Basys-3 FPGA. The GPIO demo code for the Basys-3 board works on my monitor, so I know it is possible to display it given 1280x1024 resolution, so I decided to modify their code accordingly. The full code is in a zip file which can be downloaded from that link (NERP_demo.zip).

I used values I found from this link and so the part of their code I modified from the vga640x480.v file looks like this:

// video structure constants

parameter hpixels = 1280;// horizontal pixels per line

parameter vlines = 768; // vertical lines per frame

parameter hpulse = 128;     // hsync pulse length

parameter vpulse = 7;   // vsync pulse length

parameter hbp = 216;    // end of horizontal back porch

parameter hfp = 88;     // beginning of horizontal front porch

parameter vbp = 29;         // end of vertical back porch

parameter vfp = 3;  // beginning of vertical front porch

// active horizontal video is therefore: 784 - 144 = 640

// active vertical video is therefore: 511 - 31 = 480

However, I still can't get their demo to run on my monitor. Before I changed their values, when I tried running the code, my monitor was telling me to switch to 1440x900. After I changed the values, I don't get that suggestion anymore, but the screen is still black. I don't know what to do.


1 Answer 1


You're missing an important detail -- the pixel clock for the new video mode is completely different! It requires a 109 MHz pixel clock, as compared to the 25 MHz pixel clock used for the 640x480@60Hz mode.

This 109 MHz clock cannot be derived directly from the 100 MHz input clock; you will need to use the clocking wizard to generate this signal.

  • 1
    \$\begingroup\$ In addition to that, you also need to make sure that the declared width of the counters and other internal buses is sufficient for the larger numbers. For example, a 10-bit counter cannot count to 1280. \$\endgroup\$
    – Dave Tweed
    Jun 18, 2017 at 13:19
  • \$\begingroup\$ I used the clocking wizard IP to generate a 109 MHz signal and feed it into a port dclk, but still no luck yet. \$\endgroup\$ Jun 19, 2017 at 0:16

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