I saw this HW solution in CMU Comp Arch course website. I am reading ComputerArchitecture on my own. I just have a doubt.
Here is the HW question:
Given the following code (MIPS):
MUL R3, R1, R2 ADD R5, R4, R3 ADD R6, R4, R1 MUL R7, R8, R9 ADD R4, R3, R7 MUL R10, R5, R6
Fetch (one clock cycle) Decode (one clock cycle) Execute (MUL takes 6, ADD takes 4 clock cycles). The multiplier and the adder are not pipelined. Write-back (one clock cycle)
Calculate the number of cycles it takes to execute the given code on a pipelined machine with scoreboarding and five adders and five multipliers without data forwarding.
Why the second instruction ADD R5, R4, R3 is in decode state two times? (in 3rd cycle and again in 10th cycle)
Why the third instruction ADD R6, R4, R1 did not do its DECODE state 4th cycle?