Today I was reading the datasheet and refrence manual of STM32. As others, I think we should use the power creativeness which god has gifted us to have an accurace ADC. :) Here are the datasheet and reference manual of STM32:

Datasheet & refrence manual.

So we should consider two aspects of ADC to have an accurace ADC. Hardware and software. Ok let's take a look at datasheet. I think we just should read the datasheet because it apears there is nothing about havaing an accurate ADC.(Am I right?)


There is a figure(fig 58) that tells us many things. At first we have two components out of MCU. "Rain" and "Cparasitic".


Then we should put these between MCU and the line that we are supposed to measure. Am I right? or maybe I interprate this figure incorrectly and these two are because of impedance and capacitance of line and this figure tells us another thing that we don't know. If my first suppostion is correct, so we must find out what resistor and capacitor we should choice.


First off let's check out the datasheet more. From table 59 we see that this resistor have a max value. It's 50kOhm. Why? How they say it? In the next page there is an equation named "Equation 1: Rain max formula". Ok, as the discription tells us, we can determine the maximum external impedance(Rain). The equation:


There are five parameters we should find and put in this equation to calculate the max value.

Radc : To determine this, we can use table 59. The max value for Radc is 1kOhm and I think we can use this value for every case. Fadc: We determine this when we are configuring the clock for ADC and it's pre-determined.

Cadc: Just like Radc, we can use table 59 to determine the max value for this parameter. It's 8pF.

N : Is it bit resolution? should we always take it 12?

Ts: Again, we should use table 59. It's range is 1.5 to 239.5 Am I right?

Ok, let's use this equation and do an example: Assumptions:

Ts: 1.5

Radc: 1

Fadc: 14

Cadc: 8

N: 12

And after calculation, this is what I get = -0.9986 A negetive number? why? There are a table below the discription of this equation. table 60. Rain max for Fadc=14MHz . For Ts=1.5 Rain is 0.4kOhm and I expect to get a value close to this but what I get so far is a negetive value.


A question, I still don't know, should we put a capacitor as Cparasitic between the pin of MCU and the line that we must measur? or it's the capacitance between the source of our line and our MCU and it just affects on the measurment and we should reduce Fadc. indeed it's a question to me.


Okay, let's talk about this part. If you take a look at figure 57 (ADC accuracy characteristics) you can see there are five error that I think we can remove them by software approachs.


But how to remove them? I've an idea to remove EO and EG errors. This is my approach: If we take a look at the graph accuratly, we know that there are two curves. An ideal and an actual. Everything we must do is to coincide the actual curve on the ideal one. Assume that the both curves are linear. Then we have a function X=EG*x+EO

To find EO we can connect iuput pin to ground to find the value of EO and put it in the function.

To find EG, after adding EO to x, we must find the slope of the actual curve. Then we take two sample and use this relation to find the slope. S=(Y2-Y1)/(X2-X1) and then EG=1-S

Now using X=EG*x+EO we removed these two error.

What's your opinion about my approach? is it correct? Do you have any idea to remove ET and ED and EL?

And also please answer to the question that I asked in the above passage.

  • \$\begingroup\$ A negative value for Rain indicates that RADC is already too big for that accuracy at that speed, so reduce speed, or reduce accuracy expectations. Ex is a definition of the data sheet errors. Only two measurements are needed to calibrate the ADC, fit a straight line between the two. \$\endgroup\$ – Neil_UK Jun 20 '17 at 9:39
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    \$\begingroup\$ You are asking about source impedance calculations based on varying sampling possibilities then you bring in INL, DNL, gain error and zero offset - this is too broad. Try asking a simplified question without the history of your progressing understanding embedded into your words. Keep it simple and keep God out of it. \$\endgroup\$ – Andy aka Jun 20 '17 at 9:41
  • \$\begingroup\$ @Andyaka Andy, I just tried to explain everything. anyway, everything I said is just a way to remove the errors and have an accurate ADC. I need to know how to work with ADC of my MCU. \$\endgroup\$ – Roh Jun 20 '17 at 9:51
  • \$\begingroup\$ @Andyaka Can he bring the FSM into it instead? \$\endgroup\$ – Majenko Jun 20 '17 at 9:58
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    \$\begingroup\$ "To find EO we can connect iuput pin to ground to find the value of EO and put it in the function." - Nope. You need to turn up the voltage from 0V until the ADC starts reading 1 for the first time. EO then is the difference of this voltage and 0.5*Vref/4096. \$\endgroup\$ – JimmyB Jun 20 '17 at 13:35

Rah----per the great Jim Williams in his High Frequency Amplifier Techniques book, the key to success is the environment for the analog circuit.

1) use a ground plane

2) use bypass capacitors on the AVDD for the ADC, and on the Vref supplying the charge surges needed during binary-search operation

3) keep digital currents away from the analog region of the ground plane; perhaps use slits to enforce that separation

4) ensure the sample-hold behavior has time to fully acquire the analog input, before conversion starts

5) if possible, turn off the MCU before starting a sample-hold-convert operation

6) if you have differential inputs to the ADC, maybe add this filtering circuit located directly at the Vin+ and Vin- ADC pins


simulate this circuit – Schematic created using CircuitLab


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