Today I was reading the datasheet and reference manual of STM32.
Here are the datasheet and reference manual of STM32:
We should consider two aspects of thevADC to have an accurate ADC - hardware and software.
Ok, let's take a look at datasheet. I think we just should read the datasheet because it appears there is nothing about having an accurate ADC.(Am I right?)
There is a figure (fig 58) that tells us many things. At first we have two components out of MCU. "Rain" and "Cparasitic".
Then we should put these between MCU and the line that we are supposed to measure. Am I right,or did I interpret this figure incorrectly and these two are because of impedance and capacitance of line and this figure tells us another thing that we don't know.
If my first suppostion is correct, so we must find out what resistor and capacitor we should choice.
First off let's check out the datasheet more. From table 59 we see that this resistor have a maximum value. It's 50kOhm. Why? How they say it? In the next page there is an equation named "Equation 1: Rain maximum formula". Ok, as the discription tells us, we can determine the maximum external impedance(Rain). The equation:
There are five parameters we should find and put in this equation to calculate the maximum value.
Radc: To determine this, we can use table 59. The maximum value for Radc is 1kOhm and I think we can use this value for every case.
Fadc: We determine this when we are configuring the clock for ADC and it's pre-determined.
Cadc: Just like Radc, we can use table 59 to determine the maximum value for this parameter. It's 8pF.
N: Is it bit resolution? Should we always take it to be 12?
Ts: Again, we should use table 59. Its range is 1.5 to 239.5 Am I right?
Ok, let's use this equation and do an example:
- Ts: 1.5
- Radc: 1
- Fadc: 14
- Cadc: 8
- N: 12
After calculation, I get = -0.9986
A negTive number? Why? There is a table below the discription of this equation. Table 60. Rain maximum for Fadc=14MHz . For Ts=1.5 Rain is 0.4kOhm and I expected to get a value close to this but what I get so far is a negative value.
I still don't know, if we should put a capacitor as Cparasitic between the pin of MCU and the line that we must measure, or if is the capacitance between the source of our line and our MCU and it just affects on the measurment and we should reduce Fadc. indeed it's a question to me.
Okay, let's talk about this part. If you take a look at figure 57 (ADC accuracy characteristics) you can see there are five errors that I think we can remove in software:
How can I remove them? I've an idea to remove EO and EG errors. This is my approach:
If we take a look at the graph accurately, we know that there are two curves. An ideal and an actual. All we must do is to coincide the actual curve on the ideal one. Assume that the both curves are linear. Then we have a function X=EG*x+EO
To find EO we can connect iuput pin to ground to find the value of EO and put it in the function.
To find EG, after adding EO to x, we must find the slope of the actual curve. Then we take two samples and use this relation to find the slope. S=(Y2-Y1)/(X2-X1) and then EG=1-S
Now using X=EG*x+EO we removed these two error.
What's your opinion about my approach? Is it correct? Do you have any idea to remove ET and ED and EL?
Also please answer to the question that I asked in the above passage.