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I've searched this and many other sources on Info on decoupling capacitor placement, but couldn't find any info specific enough to my current problem.

I'm currently doing a PCB Layout for a tiny, ultra-fine-pitch WLCSP microcontroller. It's 3x3mm and has 49 Balls (7x7) at 0.4mm pitch, and I'm looking at another with 36 balls (2.1x1.9mm with 0.35mm pitch). There are a couple VDD and VSS pin pairs, and unfortunately not all on the outer balls. I've tried placing all the recommended decoupling caps as close as possible to the pin-pairs, and connecting them with the shortest traces possible, as everyone recommends. However, I'm running into routing problems, and have realized that trying to keep one Capacitor on each pair of supply pins actually leads to much longer traces than if I'd just connect some of the pins to each other, so some of the supply pins would share a single capacitor.

I get that each pair of supply pins ideally should have its own capacitor. I'm not 100% sure of all the reasons why, but my understanding is it's mainly for guaranteeing shortest traces-> lowest impendance, and therefore best (local) "stabilization" of the supply voltage. And of course for seperating Analog from Digital, but since my circuit is digital only, that's not MY worry at the moment.

Now I'm wondering if this still holds true for such tiny devices, where I could, for example place a single capacitor on the bottom side, right under my component, and have all my Vdd and GND traces reach it with a single via and less than 1mm trace. 1) Why would I want to put 2 or three there? 2) Would it be better or worse if there is absolutely no space there for say the third cap anymore, and my next best option would be to place the third Capacitor next to the chip on the top layer, but require two vias and 3mm trace length to reach it, compared to a single via and 1mm trace the first or second Capacitor already under the PCB?

The supplying LDO with a bigger Capacitor (2.2 or 4.7uF will be maybe 5mm further away...)

Thanks for any helpful Info.

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    \$\begingroup\$ There should be manufacturer's application notes on recommended PCB layout and power/signal fan-out. Different Vdd pins might feed different digital blocks internally, and might have unwanted noise cross talk if just tied together. That's why they are called "de-coupling". How many layers is in your PCB design? And bigger caps are not necessarily better for the purpose of power rail decoupling. \$\endgroup\$ – Ale..chenski Jun 20 '17 at 16:08
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    \$\begingroup\$ Also, what level of technology are you already using? Are you using microvias to avoid vias under the part taking up space on the back side opposite the part? Are you using 0201 capacitors or 01005? \$\endgroup\$ – The Photon Jun 20 '17 at 16:57
  • \$\begingroup\$ Thanks for your comments... I'm still on 0402 at the moment, but will probably go to 0201 if necessary, not 01005 though. \$\endgroup\$ – thefool Jul 7 '17 at 11:18
  • \$\begingroup\$ I could not find a recommended fanout. The part is is the STM32F411CEY6, if you're interested. Yes, I understand the reasoning between the different digital blocks internally, and hence the recommendation for individual decoupling caps. However, all vdd pins will be tied together at some point, and that's the core of my question: does it really make sense to use two seperate decoupling caps, if the two Vdd lines are tied together just 1mm further away (ie there will probably be crosstalk with or without the caps)? 4 layer PCB design, btw. \$\endgroup\$ – thefool Jul 7 '17 at 11:27
  • \$\begingroup\$ Are you breaking this part out on a single layer, or are you using vias within the footprint to break traces to the backside? \$\endgroup\$ – ThreePhaseEel Feb 7 at 0:14
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You do not need to place the decoupling capacitors as close as possible (or even directly) to the power pins. Instead, be sure to use a VDD and VSS plane. Connect the microcontroller power pins as direct as possible to these planes using vias. Then, place the decoupling capacitors to a place nearby where it suits you best. Connect these decoupling capacitors directly to the planes using vias, again.

Why does this work? At the frequencies the controller is working, the power supply impedance should be low. Capacitors are low impedance in the range of approx. 100 kHz to 20 MHz. (Btw, at about some tens of MHz, the plane capacitance is slowly taking over.) But this only works if the caps are connected via a low inductance path. The idea behind placing the decoupling capacitors next to the power pins is to reduce the inductance between them and the power pins. Now, the plane has almost no inductance. Capacitor placement has almost no impact if you are using planes. We have successfully been using well defined "capacitor isles", instead of capacitor scattering, on relatively large PCBs.

Another tip: Try to place the VDD and VSS vias of the capacitor close to each other, as this reduces the inductance from capacitor to plane.

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    \$\begingroup\$ Even with a plane, a decoupler that is 10mm away from a pin may not even appear to exist depending on the signals involved. \$\endgroup\$ – Peter Smith Aug 10 '17 at 13:45
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I would add caution to @B. Kraemer's answer. While it may work if implemented properly, I have personally seen EMC problems with power plane-layers that were solved with moving decoupling capacitors more locally to reduce loop area.

I am fixing another person's design currently where partial planes were used and some decoupling was not local (about 15mm) to the Vdd/Vss pin-pairs on a microcontroller. The affected Vdd pin was dipping from 3v3 to ~700mV in just 7ns when the pin 'rung', this was causing sporadic Brown-Out-Resets. Local decoupling fixed this issue.

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In short: no, each supply pin in this BGA doesn't need its own capacitor.

I suspect you're over-optimizing this. STM32 microcontrollers are fairly forgiving in terms of decoupling needed; in practice 2-3 capacitors placed at opposite corners of the IC, anywhere within 3-5 mm of the supply pins (which also tend to be at corners), works fine.

Consider this Nucleo64 board:

enter image description here

Look at how not-close to the chip any of the capacitors are: for scale, that's a TQFP64 chip with 10x10mm body.

The decoupling caps are C23, C24, C27, C28, all 100nF in 0603 package. They're around 4-5mm from the closest power/ground pins. They could easily have been 1mm from the pins, but apparently ST didn't think that matters; they also didn't think it matters to use the lower-inductance 0402.

C22 and C26 are there for when you bypass the internal regulator and supply the core directly, typically at 1.2V. This capability is only available on some STM32 chips, see ST's AN4488, section 2.1.2. In this board they're omitted. Some Nucleo boards populate C26 only.

C30 is for analog supply, it can also be omitted although with worse analog noise. There are a few other caps here but they're not for bypassing.

This is all the caps there are: nothing on the opposite side of the PCB! Amazingly, this is probably sufficient for a worst-case usage like toggling all pins simultaneously (which I assume ST would have tested on a reference board). For non-worst-case usage, you could do a lot less.

There is probably nothing special about the same chip in a smaller package; actually it is likely to be much better because of less package/pin inductance (1). The odds are excellent that if you put your WLCSP in the middle of the same layout as the TQFP64, it will work just fine.

Practically: just put a 3-4 capacitors in 0603 package or smaller (0402 is perfect), 100nF value or greater, within a few mm of your small WLCSP microcontroller, same or opposite side of the board. Use ground and power planes, give each BGA pad its own via directly to power or ground if possible (or one via per couple of pads), and don't worry about it, it'll work.

Or if you really want to be sure: connect a good high-speed differential scope probe to the back of the power/ground vias under the chip and see if there are any glitches big enough to be a concern.

(1) okay, some packages have capacitors built in and that could vary with the package size, but that's fairly unlikely for a simple microcontroller

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    \$\begingroup\$ FWIW: C22, C25, and C26 may not be decoupling capacitors. Some STM32 microcontrollers have internal regulators; those capacitors may be placed conditionally for those parts to stabilize the regulator. \$\endgroup\$ – duskwuff Feb 6 at 21:58
  • \$\begingroup\$ @duskwuff Yes, well spotted! They are to stabilize the regulator, but you can also supply 1.2V directly to the core in which case they bypass that. I've not see a board with all of them populated; I've seen a couple with C25 only. \$\endgroup\$ – Alex I Feb 6 at 22:02
  • \$\begingroup\$ There probably aren't any with every position populated, no. ST uses a single "Nucleo-64" PCB design for all their TQFP64 parts, with parts selectively placed to configure it for part-specific pinout quirks. \$\endgroup\$ – duskwuff Feb 6 at 22:12
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Keep the extra caps, but make them into a parallel bank

The rule of thumb of "one decoupling capacitor per power pin", while sound, does not say anything about how they should be laid out on the PCB. The normal solution for BGA/BGA-like packages is to place the decoupling on the opposite side of the board from the package, allowing it to be as electrically near the power and ground pins as possible. However, given the design constraints imposed by your proposed package pitches, you will need either microvias or plugged/plated vias (i.e. proper via in pad) to break traces out to any layer other than the top.

This means that you'll need to have your decouplers at the perimeter of the package. While not ideal, it is still a tolerable state of affairs for a low-speed design. However, breakout constraints can mean you can't break out all the power/ground pairs individually to their own decouplers, either. In this case, what you can do is connect the pins in parallel, and then connect this parallel bank of pins to a matching parallel bank of decouplers at the perimeter of the package, sticking to the "one cap per power pin" rule.

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It might be overkill or not depending your chip's PDN requirements. To calculate, I have used this tool by Altera (now Intel) succesfully for most practical purposes.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/signal-power-integrity/power-distribution-network.html

For cases that require more attention (I would say %1 of the cases, though) one might use an FEM simulator like COMSOL or another.

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