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I am working on a design with 2 12V power supply, one external and one from a battery. The current needed is about 7-8A. I could have use schottky or simple diode to protect one supply from another but my objective was to manage supply, to use battery only in case of failure from external supply.

I made a small design using PMOS as switch, and it is mostly working fine if I do not connect supplies from one to another.

enter image description here

I have few points that I have trouble understanding.

  • When the switch between Vsupply and Vbat happens, LTspice shows a huge current surge drawn from one supply to another. I do not understand from where it might come from.

    enter image description here

  • I also have a voltage difference of about 1V between the output and the supply. I assume this voltage is due to the selected PMOS, but I do not understand which parameters as an impact on the design. I have selected those PMOS randomly.

If you have any suggestion regarding the selected components, I am interested.(The amplifier has to have an extremely low supply current).

  • Also, as I am low on space for my PCB, I was thinking about using SOIC Dual PMOS (such as DMP3036). But when I look at the datasheet I see a Maximum Continuous Body Diode Forward Current of 3A. I don't understand where this current impact the design. I do think that in my design, it will reduce the maxium current supplied by each source, but I am not sure. What is the difference with the drain current ?
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  • \$\begingroup\$ Re: the second point, you mean there is a voltage drop between the supply and the output? \$\endgroup\$ – nickagian Jun 21 '17 at 10:43
  • \$\begingroup\$ Yes, there is a drop between supply (the one currently used) and output. When I run the simulation without the connection between vout1 and vout 2, the drop is about 0.4V But when I connect both output, the drop increase to almost 1V. \$\endgroup\$ – Guillaume Jun 21 '17 at 11:49
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Regarding the drop between the supply and the output, it definitely comes from the \$R_{DS(on)}\$ parameter of the MOSFET. When the MOSFET is conducting, there is actually a resistor equal to \$R_{DS(on)}\$ between the drain and the source. This is usually small, but of course if the current flowing through the MOSFET is high, it creates this drop that you have observed.

What you mentioned in your comment, that there is a difference in the drop when you connect V1 with V2 and when not, this is also logical: consider what happens when you connect them together. Then you actually have both R8 and R9 as a load for the supply that is active and thus the total load is 1 Ohm instead of 2 Ohm! Thus more current is flowing through the transistor and more voltage drop is created!

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  • \$\begingroup\$ Thank you for this answer. I completly forgot about Rdson ... Regardless the inrush current, it seems to be inherent to this PMOS solution. I have the same phenomena when I reproduce this circuit using a LTC4416. I still haven't found a solution to this problem. \$\endgroup\$ – Guillaume Jun 26 '17 at 13:01
  • \$\begingroup\$ Unfortunately I cannot think of a logical explanation for the inrush current, as well. I find interesting that with the LTC4416 you get similar results... \$\endgroup\$ – nickagian Jun 26 '17 at 14:15
  • \$\begingroup\$ Thank you, I tried the design in a prototype but I could not load the circuit as much as 650mA. Even in this case, I did not have a surge current as given by LTSpice. \$\endgroup\$ – Guillaume Jul 10 '17 at 6:53

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