I need to capture the posedge of a signal (ONSWA) and output another signal (PSHOLD) high until I see another posedge of ONSWA. My solution is to use a DFF with an inverted output with ONSWA as the clock and D <= !Q. Now my question is how to properly ensure this circuit is reset when powered up. My solution is to use a RC circuit on both D and CLK but I want to know if there is a better/simpler way. My main concern the power usage--the circuit should not use too much power while in the "off" state (since it's battery powered). I also would like to avoid having PSHOLD high for a small period during reset if possible. If there's a better solution than a DFF or a better part, I would like to know that as well.
EDIT: Okay I've updated the design to use a DFF with (re)set.