I have experienced failures of RS-485 links due to magnetic induction from ~52V battery power lines running very close in parallel. Standard shielding around the RS-485 cables did not solve the problem but a clearance distance of 1 inch did. The fault probably occurred when a high current such 90A was interrupted by the opening of a relay or a breaker. I have the following questions about such cases:

  1. Standards: Is there any accepted guideline regarding clearance distances in this particular scenario? The recommendations I have seen are based on house wiring cases where there is a chance of shorting the data and power lines running through walls. Moreover, section 1.16 "Electrical Clearance" of IPC-A-620B (2012) leaves clearance spacing between cables up to design and only gives guidelines based on voltage. And while the IEC 61000-4-x tests appear to be very applicable here, they would apparently focus on protection at the transceiver level.
  2. Calculations and simulations: What is the recommended approach for calculating the induced voltage or power in such cases? Which tools are prevalent in the industry for computer simulations of such scenarios? Are such calculations followed by experimental testing?
  3. Behavior of DC current at trip: This is a more general question. For simulating scenarios like the one described, I will probably need to assume a maximum di/dt value. How fast and in what manner does a DC current terminate when its path is broken with an MCCB or a latching relay? Is it dependent on the source and load? Can waveforms from other cases be applied for this case or will I have to gather empirical data for my own system?

Standards: Is there any accepted guideline regarding clearance distances in this particular scenario?

When you take a walk outside on a mild and overcast day you cover-up because you know that the sun can still give sunburn if exposed too long. This is equivalent to moving the cables further apart (as you did).

If it gets warmer and brighter you put on a pair of shades and a hat. Warmer still, and you put on sunblock.

It's the same with EMI to data cables - you take the action that is appropriate and convenient. If that means twisted pair cables then do that.

If it means screened twisted pair then so be it. If you have to avoid earth fault currents getting through your data cables then you only terminate solidly at one end and maybe via a 10 nF at the other end.

If the common mode induced voltage is high enough to potentially push the RS485 receiver out of its common-mode input range then you use an isolated receiver (sun block).

In other words, there are precautions and you can take all of them but they come with a cost and some performance limitations (sometimes).

Calculations and simulations: What is the recommended approach for calculating the induced voltage or power in such cases?

Faraday's law of induction is a good starting point but it quickly becomes difficult to estimate induction levels when wires are twisted and the interfering source is close up (near field). So, you take the precautions that you can afford and advise installers not to do "this" and not to do "that".

Behavior of DC current at trip

You could try and model it. You know the cable type and therefore you can find out or estimate the inductance and capacitances. You can model it like a transmission line and see what di/dt you get. Plenty of simulators do this. I was using a t-line model only yesterday for a similar thing.

  • \$\begingroup\$ This is helpful. For simulating cable coupling, is there any benefit of using EM simulators such as FEKO over circuit analysis tools such LTSpice? \$\endgroup\$ Jun 23 '17 at 10:58
  • \$\begingroup\$ I don't use such tools, I estimate coupling and use a standard sim. \$\endgroup\$
    – Andy aka
    Jun 23 '17 at 11:03

I have no particular experience with such simulation, but empirically it makes sense to add a ferrite bead to limit the inrush current spike and/or a cap to absorb a voltage spike when the current stops:


simulate this circuit – Schematic created using CircuitLab

In your case specifically the cap should be useful, since your cables already provide enough inductance if they're long enough. Adding the cap will shunt most of the spike which occurs when the current stops, instead of letting that spike go into your RS-485 line via parasitic capacitance. Or, you can decrease that capacitance by increasing the gap as you have already seen.

  • \$\begingroup\$ Thank you for this perspective. My inference has been that electromagnetic induction is involved in the case of current transients as opposed to electrostatic induction (i.e. inductive coupling as opposed to capacitive coupling). As such, the Parasitic C in the schematic will only conduct if there is a voltage spike across it, an event which I have presumed to be unlikely but cannot be sure about either. Your solution may fix the problem as did the increase in clearance space. However, my goal here is to find the root cause as well as to ascertain the factor of safety. \$\endgroup\$ Jun 23 '17 at 10:09
  • 2
    \$\begingroup\$ @nbl If you suspect inductive coupling (and perhaps you're right, you know your system better than I do), adding ferrite beads may help: those will decrease the current change rate and thus the EMI in your RS-485 lines. Feel free to post your eventual findings regarding the root cause as an answer, I'll be happy to read and upvote these. \$\endgroup\$ Jun 23 '17 at 12:08

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