All switches have terminals and the terminal is like a parallel capacitance during transition. This rises with small gaps used to make lower RdsOn and lower gate resistance. MOSFETS may have smaller RdsOn than Rce of a BJT and larger T values than a BJT for some types in the same power switch category, but not all.
This is why IGBT's use MOSFET inputs and BJT outputs for very high current high voltage are popular. Yet MOSFET and IGBT designs have gone thru at least 7 generations each reducing this T constant while increasing Vout max. Thus giving more flexible choices for IGBT's and MOSFET's vs cost. (These improvements are not free, yet diverse)
A Figure of Merit (FoM) is often used by designers to choose these desirable characteristics such as this T=RC constant. It is also used to design faster turn off and slower turn on to prevent commutation "shoot thru" when both N and P channel devices are ON at the same time, using a parallel diode and R values to drive the gate faster OFF.
These FoM parameters are design specs not in the datasheets but depend on Ciss, Q , Coss values and Rg, RdsOn values.
Since the Ciss is a nonlinear dependent on Vgs, designers must decide if their gate drive like a current source ( high Z) or a voltage source (low Z) to estimate the transition time.
When you activate a switch this T=time constant depends on chip size and structural geometry and lithographic size.
In your case , you are adding Rpot to the internal Rg value and thus controlling the gate rise time with Ciss during the transition voltage region Vgs=Vth.
My rule of thumb for BGT cascaded switches is to choose an Rce that is 20x smaller or use Ic/Ib=10 to 20 which tends to be near 10% of the linear hFE.
Then for MOSFET's cascaded from high RdsON CMOS to low RdsOn power switches say from 50 mA to a 50A range load, is to consider the Rg/RdsOn ratio and take 10% of this. to determine current gain when charging Ciss at the optimal speed.
The result is RdsOn ratios from one stage to the next , I choose roughly 1% with a wide tolerance. for the reduction in RdsOn or amplify this switch ratio.
Thus optimal speed would never be a 74HCxx CMOS gate with ESR or RdsOn of 50 ohms and a power MOSFET with RdsOn with 50 mOhms (1000:1) so an intermediate driver is necessary. In future remember these ratios when choosing a design to see how it affects speed.
Your mileage may vary.