10
\$\begingroup\$

Does anyone have a source, formula, or calculator for the current carrying capacity of laser drilled micro vias? I haven't found anything great yet. I'm sure it depends on plating too. Is there a difference between copper filled, conductive filled and open or non-conductive filled?

For example I'll probably use a 5mil laser with a 2-3mil dielectric and conductive fill them and plate flat.

Oh and I did ask my vendor but haven't heard back...

edit: I don't think this is a duplicate of how much current a via can carry because a laser drilled via structure is different than a drilled via. In fact I've read in multiple places that they carry more current than a traditional via so I was looking to see if anyone had an answer.

\$\endgroup\$
7
  • \$\begingroup\$ SaturnPCB seems to have link errors, so can't give you a working link, but if you can google a functional link, download the Saturn PCB Toolkit. It's not always 100% spot on, but well within the normal margins of error for almost all the things it calculates. \$\endgroup\$
    – Asmyldof
    Jun 23, 2017 at 16:21
  • \$\begingroup\$ Thank you I have Saturn but it only has a tool for regular drilled vias as far as I can tell. I'm looking to understand the difference between those and laser vias which I've read can carry more current. \$\endgroup\$
    – confused
    Jun 23, 2017 at 16:30
  • \$\begingroup\$ @Asmyldof I was wrong Saturn has a switch to look at microvias I'll check it out. Nothing on filled or stacked vias though \$\endgroup\$
    – confused
    Jun 23, 2017 at 16:56
  • 1
    \$\begingroup\$ @laptop2d just pressed for time as always and I thought I'd ask the question and someone would show me something I'd missed in the literature or something similar. \$\endgroup\$
    – confused
    Jun 27, 2017 at 16:28
  • 1
    \$\begingroup\$ If your vendor isn't responsive with informatin about how thick the plating is in a micro via, and this is important, I think the answer is to find a vendor who is responsive. \$\endgroup\$ Jun 29, 2017 at 13:45

3 Answers 3

2
\$\begingroup\$

If this is a critical application, you should sample the board with the laser vias and then micro section a number of them and examine the cross sections under an SEM. A discussion with your board supplier about their process controls to ensure consistency in the deposition thickness is also warranted.

A less rigorous test, although perhaps a good supplementary one, is to build a board with sample vias and conduct current tests between the planes and measure the voltage drop. Statistical sampling should be used to obtain more reliable results.

\$\endgroup\$
1
  • \$\begingroup\$ True, I was hoping someone had done something similar and written a paper about it or had the experience already. \$\endgroup\$
    – confused
    Jun 23, 2017 at 16:56
1
\$\begingroup\$

Ampacity at ΔT, depends greatly on supplier quality and tolerance for dimensions, plating thickness and cost. Conductive fill is now an unnecessary cost if you simply have more plated laser holes with the better suppliers. ( yet necessary for others) or even hole in pads. ( which adds a day in cycle time)

Without specs for cost, quality, and volume, there is no single answer.

There are at least 5 different groups of suppliers for different markets of cost vs volume vs quality.

Technology is rapidly changing from UV exposed dry film to UV lithography. Choose a supplier with proven technology and experience and don't be a beta case unless you are pushing the envelope.

Here is a calculator

The best are Sierra Proto Express who say...

The current standard aspect ratio for a micro via is 0.75:1. (The micro-via diameter should be larger than the height of the material it is penetrating to the next adjacent layer.)

The first few micro designs had big fillets from the 30 micron trace to the pad. Over time, it has proven unnecessary; routing the trace direct to the pad is very strong and reliable. The extra fillets have just proven to increase image writing time and costs.

Small vias: there is a physical limit to the size of microvias. Below 50 microns (2 mils) the plating solution will not properly plate the hole wall, resulting in poor via quality. Our laser can drill holes as small as 20 microns, but we can’t plate them. The thickness of the laminate controls the minimum diameter of the vias.

Utilizing new micro circuit design technology instead of the normal printed circuit technology results in significant real estate savings.

The best pitch available today with typical 75 micron line widths is approximately 0.5mm resulting in a 75 micron (3 mil) via with 75 micron lines and a 250 micron (10 mil ) pad. The space between the pads is 225 microns (9 mils ) allowing only one 75 micron line between pads and this minimum specification is tough for most shops. enter image description here

Small vias: there is a physical limit to the size of microvias. Below 50 microns (2 mils) the plating solution will not properly plate the hole wall, resulting in poor via quality. Our laser can drill holes as small as 20 microns, but we can’t plate them. The thickness of the laminate controls the minimum diameter of the vias, with an upper limit of 2:1 for plating micro-vias.

For example, a three-mil microvia is limited to a six-mil thick laminate with respect to plating. There is also a limit of how deep our Yag laser can drill a via. As the diameter decreases so does the ability to penetrate the laminate for a clean hole. A three-mil via is limited to a four to five mils depth in FR4 and six to seven mils in a glass free laminate used in HDI applications. All about the microvia is not necessarily bad. The microvia may not be able to be as small as the traces, but we can add a sweetener to the pot since the annular ring around the microvia can be significantly smaller.

The first thing we noticed when we produced our very first micro PCB was that the vias were dead center in the pad. The design used a nine-mil pad and a three-mil via which is tight for conventional printed circuit engineering. The new, more accurate laser manufacturing method would allow as small as a five-mil pad with a three-mil via, thus saving an enormous amount of board area.

There are a few companies moving into microelectronic printed circuits; the very fine lines that used to be unavailable to the designers will now become mainstream, with the old absolute minimum line width of 75 microns (3 mils) giving way to 30 microns (1.2 mil ) or less.

track size

Micro electronic printed circuit manufacturers are unable to use the standard old dryfilm, plate and etch process to make lines under 75 microns reliably. Photolithography is the method of choice to generate these very fine lines and spaces.

Sierra Circuits can do <20 micron (0.8mil) track and gap with 2:1 ratio on laser holes for dielectric/copper thickness ratio, using Kapton. Very fine lines of 30 microns cannot, for obvious reasons, use normal one ounce copper. At Sierra we have manufactured 25 micron lines using 18 micron thick copper.

Ref's

\$\endgroup\$
-1
\$\begingroup\$

A via with standard 1.4 mil internal plating (standard foil thickness), and 1:1 ratio of periphery to depth, is ONE SQUARE of copper.

That one square has 70 degree C/watt of thermal resistance (35 degree C if heat can exit from top of via and from bottom of via into planes).

That one square has 0.000498 (call it 0.0005) milliOhms resistance.

One amp produces 0.5 milliWatt of heat (I^2 * R).

At 35 degree Cent/watt, temp rise is 17 milliDegrees. At one amp.

If your heat-rise limit is 20 degree C, you can shove 1,000 amps thru that via. If the upper and lower planes will remove the heat.

========================================

And as the 1,000 amps converges onto the periphery of that Via, heat is generated. Here is what happens

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.