I'm writing a vhdl model and I'm stuck with a problem about port declaration.
Let's say that I have an entity
entityA that instantiates N
entityB has a port,
out, with size M bits, and M can vary among all entities, so
std_logic_vector(M-1 downto 0). These ports need to be propagated outsize
entityB components would have the same port size, say FIX_M, the solution would be to use a
std_logic_vector(N*FIX_M-1 downto 0) in
entityA. My problem is that the size M can vary. The first solution that comes to my mind is to use the same solution, using instead of M a MAX_M, but in that case a lot of pins would be left unused (and for input it is a problem, right?).
Do you have a better idea? Thank you in advance.