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I've been intrigued lately by the observation that if enough inverters are placed in series the rise and fall times of output waves become invariant to the delays of the input inverter. The chain gets a characteristic wave with its own rise and fall times.

Is there someone who could ( preferably simply ) explain this to me? Because it seems rather unintuitive

Thanks in advance, Joshua

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Here is the input/output behavior of a 74HCU04, which is deliberately made without buffering (for linear applications such as crystal oscillators): enter image description here

Even with the unbuffered output you can see that the slope of the output voltage is much steeper than the slope of the input voltage. The more normal digital circuit is the 74HC04, which has a much sharper transition, such that almost in change in input voltage above or below the threshold will cause the output to go from one state to the other.

At DC these transfer curves are multiplied by stages in series. So the curve gets even sharper for multiple stages (in fact the 74HC04 is rather similar to the 74HCU04 with added stages inside for buffering). enter image description here

For AC, the switching will be dominated by the characteristics of each inverter and the loading of the output, not by the input signal rise or fall times. As each stage output slews quickly through the threshold of the next stage, that inverter will begin to switch.

TTL and CMOS inverters behave as above. ECL inverters have relatively low gain, so input rise and fall times could affect more stages.

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The reason that buffered logic has gain is precisely so that the output signals have minimal dependency on the input signals — other than their logical state, of course.

This is a very desirable feature, because it makes it easier to design larger systems from smaller modules — there are fewer details to keep track of in the interfaces.

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Inject a large sinusoid into a limiter. The output waveform rise and fall times will be set by the limiter bandwidth.

Why? the earlier gain stages provide large linear edges to the later stages; these large linear edges rapidly move across the linear response region, and the output rise and fall times become slewrate limited, this slewrate being set by that stage's operating current and junction capacitances.

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