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Let's say we have a tri-state buffer output connected to an inverter input, implemented in 7400 series CMOS chips.
If the buffer output is HI, the inverter output is LO. If the buffer output is LO, the inverter output is HI.
But what happens if the buffer output goes tri-stated (HI-Z) and we are not using a pull-up or pull-down resistor? Is the inverter input now floating and its output can vary? Or will the inverter output be stable and hold its logic level?
Do TTL chips behave differently?
The Hi-Z output and thus the inverter input will reach a voltage level which will depend on several factors. The node will have a very high impedance to ground so any noise/charge/leakage currents it picks up can affect the voltage.
If there is a clock line running nearby and that line is capacitively coupling to the node, the inverter could pick up that signal and give a clock at the output.
Without much external disturbances like clocks and noise, the leakage currents from the NMOS and PMOS transistors in the tri-state buffer will work against eachother. If for example the PMOS transistors leak slightly more than the NMOS transistors then chances are the Hi-Z node will go up in voltage and eventually reach the supply voltage. But at a different temperature or same model chip but from a different manufacturer or even same model from the same manufacturer but from a different batch of chips the opposite could also happen (NMOS leaking more I mean). This is unpredictable so we want to avoid that always !
Anyway, it is bad practice to leave a CMOS gate input floating like that. So you'd never find this situation in a properly designed circuit. What most circuit designers do is define the voltage in Hi-Z mode by using a pull down or pull up resistor.
In TTL a Hi-Z is usually interpreted as 1 (one). But again, this is bad practice and it is better design practice to define all inputs properly just like in CMOS logic.
Charge injected during the switching from Driven to TriState will make the buss voltage indeterminate.
