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Let's say we have a tri-state buffer output connected to an inverter input, implemented in 7400 series CMOS chips.

If the buffer output is HI, the inverter output is LO. If the buffer output is LO, the inverter output is HI.

But what happens if the buffer output goes tri-stated (HI-Z) and we are not using a pull-up or pull-down resistor? Is the inverter input now floating and its output can vary? Or will the inverter output be stable and hold its logic level?

Do TTL chips behave differently?

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  • \$\begingroup\$ Nitpick: there is no such thing as "7400 series CMOS" -- 7400 is TTL. Do you mean 74HC series? \$\endgroup\$ – duskwuff Jun 26 '17 at 1:00
  • \$\begingroup\$ @duskwuff 74hc is part of the 7400 series Mr. Wise Guy! \$\endgroup\$ – uzumaki Jun 26 '17 at 21:49
  • \$\begingroup\$ But then there's no single answer. These behaviors, especially for marginal or floating signals, have changed significantly across different logic families. \$\endgroup\$ – duskwuff Jun 26 '17 at 21:52
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The Hi-Z output and thus the inverter input will reach a voltage level which will depend on several factors. The node will have a very high impedance to ground so any noise/charge/leakage currents it picks up can affect the voltage.

If there is a clock line running nearby and that line is capacitively coupling to the node, the inverter could pick up that signal and give a clock at the output.

Without much external disturbances like clocks and noise, the leakage currents from the NMOS and PMOS transistors in the tri-state buffer will work against eachother. If for example the PMOS transistors leak slightly more than the NMOS transistors then chances are the Hi-Z node will go up in voltage and eventually reach the supply voltage. But at a different temperature or same model chip but from a different manufacturer or even same model from the same manufacturer but from a different batch of chips the opposite could also happen (NMOS leaking more I mean). This is unpredictable so we want to avoid that always !

Anyway, it is bad practice to leave a CMOS gate input floating like that. So you'd never find this situation in a properly designed circuit. What most circuit designers do is define the voltage in Hi-Z mode by using a pull down or pull up resistor.

In TTL a Hi-Z is usually interpreted as 1 (one). But again, this is bad practice and it is better design practice to define all inputs properly just like in CMOS logic.

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    \$\begingroup\$ Using traditional TTL an open input is seen as a '1' not a zero. This is because the input sources current into the output (0.4mA in original TTL) so pulls the input up. The voltage on an open input will rise to about 1.3v. Because it only pulls it up to the threshold it is a very unreliable level and can easily be affected by noise so should no be relied upon. \$\endgroup\$ – Kevin White Jun 25 '17 at 21:19
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    \$\begingroup\$ @KevinWhite indeed you are correct. Never used TTL so didn't realize my error. I updated my answer. \$\endgroup\$ – Bimpelrekkie Jun 26 '17 at 7:03
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    \$\begingroup\$ CMOS floating inputs is not only bad practice, it can cause the IC to fry. \$\endgroup\$ – Peter Smith Jun 26 '17 at 7:27
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Charge injected during the switching from Driven to TriState will make the buss voltage indeterminate.

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