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I need help in understanding the solution from solution manual.
The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition).
The question is about instruction pipelining.

The question

Consider two instruction sequences:
enter image description here
Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).

The solution from solution manual

With ALU-ALU-only forwarding, an ALU instruction can forward to the next instruction, but not to the second-next instruction (because that would be forwarding from MEM to EX). A load cannot forward at all, because it determines the data value in MEM stage, when it is too late for ALU-ALU forwarding. We have: enter image description here

Doubts

  1. The question asks to add NOPs. But I dont see single NOP in the solution given.

  2. In the solution it says "A load cannot forward at all, because it determines the data value in MEM stage, when it is too late for ALU-ALU forwarding.". Then how there can be "ALU-ALU forwarding of R4 from I2" in isntruction sequence 1?

  3. I dont get the meaning of the question itself. Does it mean to replace ALU-ALU forwarding with NOPs and keep MA-EX forwarding untouched?

  4. This link gives solution to 2nd instruction sequence as follows:
    enter image description here
    while this chegg link gives its solution as follows:
    enter image description here
    Whats true?

(There are other resources giving other instruction sequences, like ppts and pdf from different university courses, but none of them give satisfactory logical solution. I did not give them here to avoid further confusion.)

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If I'm reading the question correctly, it does not mean that ALU-ALU forwarding is forbidden in an LW instruction but rather the new result from the load will not be forwarded from the MEM stage, thus you now have a data hazard between I2 and I3 in a. (Edit: the MEM forwarding is actually moot here since the EX stage of I3 happens at the same time as MEM stage of I2 so any forwarding will be too late).

If this is a classic RISC pipeline then you simply need to add (edit: two to account for both MEM and WB) NOP between the LW and the ADD to avoid the data hazard here.

The solutions you found are true only of ALU-ALU forwarding does not occur.

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  • \$\begingroup\$ If ALU-ALU forwarding means EX-EX forwarding and if I understand the topic correctly, I guess that their cannot be ALU-ALU (EX-EX) forwarding at all from LW instruction to next instruction, since in EX stage of LW instruction, ALU calculates the effective address of the operand to be loaded from memory to the register. This operand becomes available only in MEM stage. So EX-EX forwarding is not possible. Hence I feel we cannot say that the question "does not mean that ALU-ALU forwarding is forbidden in an LW instruction" \$\endgroup\$ – anir123 Jun 26 '17 at 9:08
  • \$\begingroup\$ Do you mean we need to add two NOPs after LW? If yes, thats right because the other question asks to do so (add NOPs to eliminate any data dependency hazards) and the solution manual gives says the same (two NOPs after LW). But thats other question, not this question. \$\endgroup\$ – anir123 Jun 26 '17 at 9:10
  • \$\begingroup\$ Reading this question again, it says "Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage)." It says "if there is ALU-ALU forwarding only", so does that mean we shouldnt be bothered about problem with LW since it requires MEM-ID forwarding? and we should only think of instruction sequence (b)? \$\endgroup\$ – anir123 Jun 26 '17 at 9:13
  • \$\begingroup\$ Bro, no comment? \$\endgroup\$ – anir123 Jul 1 '17 at 16:04
  • \$\begingroup\$ Sorry, I was offline for a few days. For LW the problem is that needs forwarding from MEM to ID in order for the ADD to do its work, but as you said MEM-ID forwarding is not allowed therefore you need to add the requisite NOPs for the memory load and register write back to complete. \$\endgroup\$ – Tony K Jul 2 '17 at 23:03

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